Integrated
Circuit
Systems, Inc.
ICS9148-26
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
General Description
The
ICS9148-26
generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Features include two CPU, six PCI and fourteen SDRAM clocks.
Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.5% or ±1.5% modulation to reduce the
EMI. Serial programming I
2
C interface allows changing
functions, stop clock programing and Frequency selection.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up. It is not recommended to use I/O
dual function pin for the slots (ISA, PIC, CPU, DIMM). The
add on card might have a pull up or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates into 20pF.
Features
3.3V outputs: SDRAM, PCI, REF, 48/24MHz
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.2 ns.
No external load cap for C
L
=18pF crystals
±250 ps CPU, PCI clock skew
250ps (cycle to cycle) CPU jitter @ 66.66MHz
Smooth frequency switch, with selections from 50 to
133 MHz CPU.
I
2
C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<6ns propagation delay SDRAM form Buffer Input
Pin Configuration
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:4)
VDD3 = SDRAM (0:13), supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:1)
9148-26 Rev D 07/23/98
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-26
Pin Descriptions
PIN NUMBER
1
PIN NAME
VDD1
TYPE
PWR
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the
STRONGER buffer for ISA BUS loads
2
3,9,16,22,
33,39,45
4
5
6,14
7
8
10, 11, 12, 13
15
18
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38,40,41
19,30,36
23
24
25
26
27
43, 44
42
46
17
REF0
GND
X1
X2
VDD2
PCICLK_F
MODE
1 , 2
PCICLK0
PCICLK(1:4)
BUFFER IN
PCI_STOP#
1
SDRAM (0:13)
VDD3
SDATA
SCLK
24MHz
FS1
1 , 2
48MHz
FS0
1 , 2
VDD4
CPUCLK(0:1)
VDDL2
REF1
FS2
1 , 2
CPU_STOP#
1
OUT
PWR
IN
OUT
PWR
OUT
IN
OUT
OUT
IN
IN
OUT
PWR
IN
IN
OUT
IN
OUT
IN
PWR
OUT
PWR
OUT
IN
IN
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
PCI clock output.
PCI clock outputs.
Input to Fanout Buffers for SDRAM outputs.
Halts PCICLK(0:4) clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
(Pins 17, 18 SDRAM output only if MODE=High)
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Supply for SDRAM (0:13) and CPU PLL Core, nominal 3.3V.
Data input for
I
2
C serial input, 5V tolerant input
Clock input of
I
2
C input, 5V tolerant input
24MHz output clock
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:1), either 2.5V or 3.3V nominal
14.318 MHz reference clock.
Frequency select pin. Latched Input
Halts CPUCLK (0:1) clocks at logic 0 level, when input low (in
Mobile Mode, MODE=0)
IOAPIC clock output. 14.318 MHz Powered by VDDL1.
Supply for IOAPIC, either 2.5 or 3.3V nominal
47
48
IOAPIC
VDDL1
OUT
PWR
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS9148-26
Mode Pin - Power Management Input Control
MODE, Pin 7
(Latched Input)
0
1
Pin 17
CPU_STOP#
(INPUT)
SDRAM11
(OUTPUT)
Pin 18
PCI_STOP#
(INPUT)
SDRAM10
(OUTPUT)
Power Management Functionality
CPU_STOP#
PCI_STOP#
CPUCLK
Outputs
Stopped Low
Running
Running
Stopped Low
PCICLK
(0:4)
Running
Running
Stopped Low
Stopped Low
PCICLK_F,
REF,
24/48MHz
and SDRAM
Running
Running
Running
Running
Crystal
OSC
Running
Running
Running
Running
VCO
0
1
1
0
1
1
0
0
Running
Running
Running
Running
Functionality
V
DD
1,2,3 = 3.3V±5%, V
DDL
1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS2
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
CPU
(M H z)
100.2
133.3
1
112.0
1
103
6 6 .8
8 3 .3
75
50
P C IC LK
(M H z)
33.3 (C PU/3)
33.3 (C PU/4)
1
37.3 (C PU/3)
1
34.3 (C PU/3)
33.4 (C PU/2)
41.65 (C PU/2)
37.5 (C PU/2)
25 (C PU/2)
R EF, IO A P IC
(M H z)
1 4 .3 1 8
1 4 .3 1 8
1 4 .3 1 8
1 4 .3 1 8
1 4 .3 1 8
1 4 .3 1 8
1 4 .3 1 8
1 4 .3 1 8
Note1.
Performance not guaranteed
3
ICS9148-26
General I
2
C serial interface information
A.
For the clock generator to be addressed by an I
2
C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
Clock Generator
Address (7 bits)
+ 8 bits dummy
command code
+ 8 bits dummy
Byte count
A(6:0) & R/W#
D2
(H)
B.
ACK
ACK
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
The clock generator is a slave/receiver I
2
C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above)
Read-Back will support Intel PIIX4 "Block-Read" protocol,
with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator
Address (7 bits)
Byte Count
Readback
A(6:0) & R/W#
D3
(H)
C.
D.
E.
F.
ACK
ACK
Then Byte 0, 1, 2, etc. in
sequence until STOP.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled
output state).
G
..
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Description
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit6 Bit5 Bit4
CPU clock
PCI
33.3 (CPU/3)
111
100.2
33.3
2
110
133.3
2
37.3
2
101
112.0
2
103
34.3 (CPU/3)
100
011
66.8
33.4 (CPU/2)
010
83.3
41.65(CPU/2)
001
75
37.5 (CPU/2)
000
50
25 (CPU/2)
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
PWD
0
Bit 6:4
Note1
Note1.
Default at Power-up will be for
latched logic inputs to define
frequency. Bits 4, 5, 6 are default
to 000, and if bit 3 is written to a 1
to use Bits 6:4, then these should
be defined to desired frequency at
same write cycle.
Note2.
Performance not guaranteed
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
Note:
PWD = Power-Up Default
I
2
C is a trademark of Philips Corporation
4
ICS9148-26
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
SDRAM13 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
14
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
26
25
-
21,20,18,17
32,31,29,28
38,37,35,34
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
48MHz (Act/Inact)
24 MHz (Act/Inact)
(Reserved)
SDRAM (8:11) (Active/Inactive)
(SDRAM 10, 11 only in Desktop Mode, MODE=1)
SDRAM (4:7) (Active/Inactive)
SDRAM (0:3) (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
5
京公网安备 11010802033920号
EEWORLD
