Integrated
Circuit
Systems, Inc.
ICS950223
Programmable Timing Control Hub™ for P4™
Recommended Application:
Brookdale and Brookdale-G chipset with P4 processor.
Output Features:
•
3 - Pairs of differential CPU clocks
(differential current mode)
•
3 - 3V66 @ 3.3V
•
10 - PCI @ 3.3V
•
1 - 48MHz @ 3.3V fixed
•
2 - REF @ 3.3V, 14.318MHz
•
1 - 48_66MHz selectable @ 3.3V fixed
•
1 - 24_48MHz selectable @ 3.3V
Features/Benefits:
•
QuadRom
TM
frequency selection.
•
Programmable output frequency.
•
Programmable asynchronous 3V66 & PCI frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watchdog safe frequency.
•
Support I
2
C Index read/write and block read/write
operations.
•
Uses external 14.318MHz reference input.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
Pin Configuration
*MULTSEL1/REF1 1
VDDREF 2
X1 3
X2 4
GND 5
*FS2/PCICLK0 6
*FS3/PCICLK1 7
**SEL48_24#/PCICLK2 8
VDDPCI 9
PCICLK4 11
PCICLK5 12
GND 13
PCICLK6 14
PCICLK7 15
PCICLK8 16
PCICLK9 17
VDDPCI 18
Vttpwr_GD# 19
RESET# 20
~
48 REF0/MULTSEL0**
47 GNDREF
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 GNDCPU
42 PD#*
41 CPUCLKT0
40 CPUCLKC0
ICS950223
*FS4/PCICLK3 10
39 VDDCPU
38 CPUCLKT1
37 CPUCLKC1
36 GNDCPU
35 IREF
34 AVDD
33 GND
32 VDD3V66
31 3V66_0
30 3V66_1
29 GND
28 3V66_2
27 3V66_3_48MHz/Sel66_48#**
26 SCLK
25 SDATA
GND 21
*FS0/48MHz 22
AVDD48 24
*FS1/24_48MHz 23
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~
This output has 2X drive strength
Frequency Table
Bit4
FS4
0
0
0
0
0
0
0
0
0
0
Bit3
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit2
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit0
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
102.00
105.00
108.00
111.00
114.00
117.00
120.00
123.00
126.00
130.00
136.00
140.00
144.00
148.00
152.00
156.00
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
100.20
133.60
200.40
66.67
100.00
200.00
133.33
3V66
MHz
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
72.00
74.29
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
66.64
68.00
70.00
72.00
74.00
76.00
66.80
66.80
66.80
66.80
66.67
66.67
66.67
66.67
PCI
MHz
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
36.00
37.14
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
33.32
34.00
35.00
36.00
37.00
38.00
33.40
33.40
33.40
33.40
33.34
33.33
33.33
33.33
Block Diagram
PLL2
/2
48MHz
24_48MHz
REF (1:0)
3V66
DIVDER
0
0
0
0
0
0
1
1
X1
X2
XTAL
OSC
3V66_48MHz
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (9:0)
3V66 (2:0)
RESET#
I REF
PLL1
Spread
Spectrum
Control
Logic
CPU
DIVDER
3
3
1
1
1
PCI
DIVDER
10
1
1
PD#
MULTSEL(1:0)
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
SEL 48_24#
SEL 66_48#
0496C—05/06/05
3V66
DIVDER
1
1
1
1
1
1
1
1
1
4
Config.
Reg.
Integrated
Circuit
Systems, Inc.
ICS950223
General Description
The
ICS950223
is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory.
It provides all necessary clock signals for such a system.
The
ICS950223
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first
to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's
newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I
2
C
interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal
spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates
ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can
configure output frequency with resolution up to 0.1MHz increment. With all these programmable features ICS's, TCH makes mother
board testing, tuning and improvement very simple.
Pin Description
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN
NAME
*MULTSEL1/REF1
VDDREF
X1
X2
GND
*FS2/PCICLK0
*FS3/PCICLK1
**SEL48_24#/PCICLK2
VDDPCI
*FS4/PCICLK3
PCICLK4
PCICLK5
GND
PCICLK6
PCICLK7
PCICLK8
PCICLK9
VDDPCI
Vttpwr_GD#
RESET#
GND
~*FS0/48MHz
*FS1/24_48MHz
AVDD48
PIN
TYPE
I/O
DESCRIPTION
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
PWR Ref, XTAL power supply, nominal 3.3V
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin.
I/O Frequency select latch input pin / 3.3V PCI clock output.
I/O Frequency select latch input pin / 3.3V PCI clock output.
I/O
PWR
I/O
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
Latched select input for 48/24MHz output. 0=24MHz, 1 = 48MHz / 3.3V PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
IN
valid and are ready to be sampled. This is an active low input.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
OUT
This signal is active low.
PWR Ground pin.
I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
I/O Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive
0496C—05/06/05
2
Integrated
Circuit
Systems, Inc.
ICS950223
Pin Description (Continued)
PIN PIN
#
NAME
PIN
TYPE
I/O
IN
I/O
OUT
PWR
OUT
OUT
PWR
PWR
PWR
OUT
PWR
OUT
OUT
PWR
OUT
OUT
IN
PWR
OUT
OUT
PWR
PWR
I/O
DESCRIPTION
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Selectable 66.66MHz, 48MHz clock output / Select input for 66.66/48MHz output.
0=48mHz, 1 = 66.66MHz
3.3V 66.66MHz clock output
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V Analog Power pin for Core PLL
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
Ground pin for the CPU outputs
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
Ground pin for the CPU outputs
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the REF outputs.
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz
reference clock.
25 SDATA
26 SCLK
27 3V66_3_48MHz/Sel66_48#**
28
29
30
31
32
33
34
3V66_2
GND
3V66_1
3V66_0
VDD3V66
GND
AVDD
35 IREF
36 GNDCPU
37 CPUCLKC1
38 CPUCLKT1
39 VDDCPU
40 CPUCLKC0
41 CPUCLKT0
42 PD#*
43 GNDCPU
44 CPUCLKC2
45 CPUCLKT2
46 VDDCPU
47 GNDREF
48 REF0/MULTSEL0**
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive
0496C—05/06/05
3
Integrated
Circuit
Systems, Inc.
ICS950223
Maximum Allowed Current
Condition
Powerdown Mode
(PWRDWN# = 0)
Full Active
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
40mA
360mA
CPUCLK Swing Select Functions
MULTSEL0
0
0
0
0
1
1
1
1
MULTSEL1
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Reference R,
Iref=
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Output
Current
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
Voh @ Z,
Iref=2.32mA
0.71V @ 60
0.59V @ 50
0.85V /2 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
0
0
0
0
1
1
1
1
0496C—05/06/05
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
0.5V @ 20
1.05V @ 30
0.84V @ 20
4
Integrated
Circuit
Systems, Inc.
ICS950223
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
ACK
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page
.
0496C—05/06/05
5
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