DATASHEET
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
9FGP202A
General Description
The 9FGP202A is a peripheral clock for Intel Server. It is
driven with a 25MHz crystal and generates CPU outputs up
to 400MHz. An SMBus interface allows full control of the
device.
Features/Benefits
•
Selectable SMBus Address – D0/D1 or C0/C1
•
Spread Spectrum capability on CPU and DOT 96MHz
•
clocks
SMBus Control:
– M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
– Outputs can be disabled via pins or SMBus
Recommended Application
Peripheral Clock for Intel Server
Output Features
•
•
•
•
•
•
1 - 0.7V current-mode differential CPU pair
8 - 50MHz output
1 - DOT 96MHz output
1 - 33.33MHz output
1 - 32.768KHz output
2 - 25MHz REF outputs
Key Specifications
•
Exact synthesis on CPU, RMII and 33.33MHz clocks
•
+/- 100ppm frequency accuracy on remaining clocks
Block Diagram
25MHz(1:0)
X1_25
X2_25
XTAL
CPU PLL
(SPREAD
CAPABLE)
CPUCLK
VttPwr_GD/PD#
OE_CPU
OE_96
OE_RMIIA
OE_RMIIB
SMBADR
SMBDAT
SMBCLK
CONTROL
LOGIC
DOT PLL
(SPREAD
CAPABLE)
DOT96SS
33.33MHz
FIXED
PLL
DIVIDERS
8
RMII(7:0)
DIVIDERS
32.768KHz
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
1
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Pin Configuration
VttPwr_GD/PD#
OE_RMIIA
30
29
28
27
26
25
24
23
22
21
X1_25
GNDREF
X2_25
25
MHz
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
2
GNDRMII
VDDRMII
SMBDAT
SMBCLK
RMII0
RMII1
40 39 38 37 36 35 34 33 32 31
GND
VDD96
DOT96SST
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
1
2
3
4
5
6
7
8
9
10
IREF
32.768KHz
VDD32K
OE_RMIIB
RMII4
RMII5
GND RMII
VDDRMII
RMII6
RMII7
VDD33
33.33MHZ/**SMBADR
GND 33
9FGP202
11 12 13 14 15 16 17 18 19 20
GND32K
25MHZ_1
25MHz_0
VDDREF
40-MLF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
SMBus Address Selection
SMBADR
*SMBADR = 0
D0/D1
* Default value
SMBADR = 1
C0/C1
Power Supply Pins
Pin Number
Description
VDD
GND
9
10
CPUCLK output
2
1
DOT96SS output
26,34
27,35
50 MHz RMII outputs
23
21
33.33MHz output
12
14
32.768KHz output
15
18
XTAL, REF outputs
Note: All VDD should be connected to a common power rail with proper filtering
and decoupling.
Functionality
CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS
MHz
MHz
Byte0 Bit2 Byte0 Bit1 Byte0 Bit0
0
0
0
266.67
96.00
0
0
1
133.33
96.00
0
1
0
200.00
96.00
1
1
166.67
96.00
0
1
0
0
333.33
96.00
1
0
1
100.00
96.00
1
1
0
400.00
96.00
1
1
1
Reserved
96.00
P ower up default is highlighted.
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
RMII
MHz
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
RMII3
RMII2
32.768
KHz
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
9FGP202A
REV D 070511
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PIN NAME
GND
VDD96
DOT96SST
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
IREF
VDD32K
32.768KHz
GND32K
VDDREF
25MHz_0
25MHZ_1
GNDREF
X1_25
X2_25
GND33
33.33MHZ/**SMBADR
VDD33
RMII7
RMII6
VDDRMII
GNDRMII
RMII5
RMII4
OE_RMIIB
OE_RMIIA
RMII3
RMII2
VDDRMII
GNDRMII
RMII1
RMII0
SMBCLK
SMBDAT
VttPwr_GD/PD#
PIN TYPE
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
OUT
PWR
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
DESCRIPTION
Ground pin.
Power pin for the DOT96 cloc ks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock .
Complement clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
Ac tive high input for enabling 96Hz outputs.
1 = enable output(s ), 0 = tri-state output(s)
Ac tive high input for enabling CPU DIFF pairs.
1 = enable output(s ), 0 = tri-state output(s)
True clock of differential pair CPU outputs. These are c urrent mode outputs. External resistors are
required for voltage bias .
Complementary c lock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision res istor tied to ground in order to establish the appropriate current. 475
ohms is the standard v alue.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Ground pin for the REF outputs .
Crystal input, Nominally 25.00MHz.
Crystal output, Nominally 25.00MHz .
Ground pin for the 33.33MHz outputs
33.33MHz clock output / SMBus address select bit.
Power pin for the 33.33MHz outputs , nominal 3.3V
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Ac tive high input for enabling RMII(7:4) outputs.
1 = enable output(s ), 0 = low
Ac tive high input for enabling RMII(3:0) outputs.
1 = enable output(s ), 0 = low
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and
are ready to be sampled. This is an active high input. / Asynchronous activ e low input pin used to
power down the devic e into a low power state.
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
3
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Drive Strengths
9FGP202A
The singled-ended outputs of the 9FGP202A default to either a drive strength of 2 loads or a drive strength of 1 load.
Alternate drive strengths can be selected via the SMBus. Using the correct resistor value can properly terminate the output
to the transmission line without having to change the default drive strengths via the SMBus. The default drive strengths for
the single ended outputs are show below, as are the suggested termination resistors for the above topologies. All values
assume Zo = 50 ohms:
Default Drive Strength Table
Default Drive
RMII
1 Load
33.33MHz
2 Loads
25Mhz
2 Loads
32.768KHz
2 Loads
Optional Drive
2 Loads
1 Load
1 Load
1 Load
Series Termination Resistor Values
Series Resistor Series Resistor
Output Drive
(Rs) for driving 1 (Rs) for driving 2
Load
Loads
Strength
1 Load
33 ohms
N/A
2 Loads
43 ohms
22 ohms
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
4
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Truth Table 1: VttPwr_GD/PD# and OE_96
VttPwr_GD/PD#
OE_96
Clocks
Pin 40
Pin 5
0
0
All clocks are powered down
0
1
All clocks are powered down
1
0
All clocks are enabled except DOT96SS
1
1
*All clocks are enabled including DOT96SS
*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)
Truth Table 2: VttPwr_GD/PD# and OE_CPU
VttPwr_GD/PD#
OE_CPU
Clocks
Pin 40
Pin 6
0
0
All clocks are powered down
0
1
All clocks are powered down
1
0
All clocks are enabled except CPUCLK
1
1
*All clocks are enabled including CPUCLK
*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)
Table 1: CPU Spread and Frequency Selection
CPU
SS_EN
Byte 0
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CPU
FS2
Byte 0
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CPU
FS1
Byte 0
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CPU
FS0
Byte 0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
Down
Spread %
0%
0%
0%
0%
0%
0%
0%
0%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
5
9FGP202A
REV D 070511
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