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IDT7024S35JB

Description
Dual-Port SRAM, 4KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84
Categorystorage    storage   
File Size287KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT7024S35JB Overview

Dual-Port SRAM, 4KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84

IDT7024S35JB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeLCC
package instructionQCCJ, LDCC84,1.2SQ
Contacts84
Reach Compliance Codenot_compliant
ECCN code3A001.A.2.C
Maximum access time35 ns
Other features4K X 16 DUAL PORT SRAM
I/O typeCOMMON
JESD-30 codeS-PQCC-J84
JESD-609 codee0
length29.3116 mm
memory density65536 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals84
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize4KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC84,1.2SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum seat height4.57 mm
Maximum standby current0.00003 A
Minimum standby current4.5 V
Maximum slew rate0.3 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width29.3116 mm
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7024S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7024 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Devices are capable of withstanding greater than 2001V
electrostatic discharge.
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R(1,2)
Address
Decoder
12
A
11L
A
0L
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs
are non-tri-stated
push-pull.
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R(2)
2740 drw 01
M/
S
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2740/6
6.15
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