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IDT7381L16G

Description
Bit-Slice Processor, 16-Bit, CMOS, CPGA68, CAVITY-UP, PGA-68
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size72KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT7381L16G Overview

Bit-Slice Processor, 16-Bit, CMOS, CPGA68, CAVITY-UP, PGA-68

IDT7381L16G Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instructionPGA,
Contacts68
Reach Compliance Codeunknown
ECCN code3A001.A.3
Other features2 X 16 BIT DATA INPUT BUS; 3 CONTROL PINS TO SELECT OPERATION; ICC SPECIFIED @ 10MHZ
maximum clock frequency62.5 MHz
External data bus width16
JESD-30 codeS-CPGA-P68
JESD-609 codee3
length29.464 mm
Number of terminals68
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum slew rate76 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width29.464 mm
uPs/uCs/peripheral integrated circuit typeBIT-SLICE MICROPROCESSOR
HIGH-SPEED
4K x 9 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7014S
FEATURES:
• True Dual-Ported memory cells which allow simultaneous
access of the same memory location
• High-speed access
— Military: 20/25/35ns (max.)
— Commercial: 12/15/20/25ns (max.)
• Low-power operation
— IDT7014S
Active: 900mW (typ.)
• Fully asynchronous operation from either port
• TTL-compatible; single 5V (±10%) power supply
• Available in 52-pin PLCC and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7014 is an extremely high-speed 4K x 9 Dual-Port
Static RAM designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself
to high-speed applications which do not need on-chip arbitra-
tion to manage simultaneous access.
The IDT7014 provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. See functional description.
The IDT7014 utilitizes a 9-bit wide data path to allow for
parity at the user's option. This feature is especially useful in
data communication applications where it is necessary to use
a parity bit for transmission/reception error checking.
Fabricated using IDT’s high-performance technology, the
IDT7014 Dual-Ports typically operate on only 900mW of
power at maximum access times as fast as 12ns.
The IDT7014 is packaged in a 52-pin PLCC and a 64-pin
thin plastic quad flatpack (TQFP).
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
R/
W
R
OE
L
I/O
0L
- I/O
8L
COLUMN
CONTROL
COLUMN
CONTROL
OE
R
I/O
0R
- I/O
8R
A
0L
- A
11L
LEFT SIDE
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
RIGHT SIDE
ADDRESS
DECODE
LOGIC
A
0R
- A
11R
2528 drw 01
The IDT logo is a registereed trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2528/6
6.11
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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