Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I
2
C, low pin count
83C751/87C751
DESCRIPTION
The Philips 83C751/87C751 offers the advantages of the 80C51
architecture in a small package and at low cost.
The 8XC751 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up sensitivity.
The 8XC751 contains a 2k
×
8 ROM (83C751) EPROM (87C751), a
64
×
8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a
five-source, fixed-priority level interrupt structure, a bidirectional
inter-integrated circuit (I
2
C) serial bus interface, and an on-chip
oscillator.
The on-board inter-integrated circuit (I
2
C) bus interface allows the
8XC751 to operate as a master or slave device on the I
2
C small
area network. This capability facilitates I/O and RAM expansion,
access to EEPROM, processor-to-processor communication, and
efficient interface to a wide variety of dedicated I
2
C peripherals.
PIN CONFIGURATIONS
P3.4/A4 1
P3.3/A3 2
P3.2/A2/A10 3
P3.1/A1/A9 4
P3.0/A0/A8 5
P0.2/V
PP
6
P0.1/SDA/OE–PGM 7
P0.0/SCL/ASEL
RST
8
9
PLASTIC
DUAL
IN-LINE
PACKAGE
AND
SHRINK
SMALL
OUTLINE
PACKAGE
24 V
CC
23 P3.5/A5
22 P3.6/A6
21 P3.7/A7
20 P1.7/T0/D7
19 P1.6/INT1/D6
18 P1.5/INT0/D5
17 P1.4/D4
16 P1.3/D3
15 P1.2/D2
14 P1.1/D1
13 P1.0/D0
X2 10
X1 11
V
SS
12
FEATURES
•
80C51 based architecture
•
Inter-Integrated Circuit (I
2
C) serial bus interface
•
Small package sizes
–
24-pin DIP (300 mil “skinny DIP”)
–
24-pin Shrink Small Outline Package
–
28-pin PLCC
4
5
1
26
25
PLASTIC
LEADED
CHIP
CARRIER
11
12
Pin
1
2
3
4
5
6
7
8
9
Function
P3.4/A4
P3.3/A3
P3.2/A2/A10
P3.1/A1/A9
NC*
P3.0/A0/A8
P0.2/V
PP
P0.1/SDA/OE-PGM
P0.0//SCLASEL
18
Pin
19
20
21
22
23
24
25
26
27
28
Function
P1.4/D4
P1.5/INT0/D5
NC*
NC*
P1.6/INT1/D6
P1.7/T0/D7
P3.7/A7
P3.6/A6
P3.5/A5
V
CC
19
•
87C751 available in one-time programmable plastic packages
•
Wide oscillator frequency range
•
Low power consumption:
–
Normal operation: less than 11mA @ 5V, 12MHz
–
Idle mode
–
Power-down mode
PinFunction
10
NC*
11
RST
12
X2
13
X1
14
V
SS
15
P1.0/D0
16
P1.1/D1
17
P1.2/D2
18
P1.3/D3
•
2k
×
8 ROM (83C751)
* DO NOT CONNECT
2k
×
8 EPROM (87C751)
SU00315
•
64
×
8 RAM
•
16-bit auto reloadable counter/timer
•
Fixed-rate timer
•
Boolean processor
•
CMOS and TTL compatible
•
Well suited for logic replacement, consumer and industrial
applications
•
LED drive outputs
1998 May 01
2
853-0599 19326
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I
2
C, low pin count
83C751/87C751
ORDERING INFORMATION
ROM
S83C751–1N24
S83C751–2N24
S83C751–4N24
S83C751–5N24
S83C751–1A28
S83C751–2A28
S83C751–4A28
S83C751–5A28
S83C751–1DB
S83C751–4DB
EPROM
1
S87C751–1N24
S87C751–2N24
S87C751–4N24
S87C751–5N24
S87C751–1A28
S87C751–2A28
S87C751–4A28
S87C751–5A28
S87C751–1DB
S87C751–4DB
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
TEMPERATURE RANGE
°
C
AND PACKAGE
0 to +70, Plastic Dual In-line Package
–40 to +85, Plastic Dual In-line Package
0 to +70, Plastic Dual In-line Package
–40 to +85, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Leaded Chip Carrier
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Leaded Chip Carrier
0 to +70, Shrink Small Outline Package
0 to +70, Shrink Small Outline Package
FREQUENCY
3.5 to 12MHz
3.5 to 12MHz
3.5 to 16MHz
3.5 to 16MHz
3.5 to 12MHz
3.5 to 12MHz
3.5 to 16MHz
3.5 to 16MHz
3.5 to 12MHz
3.5 to 16MHz
DRAWING
NUMBER
SOT222-1
SOT222-1
SOT222-1
SOT222-1
SOT261-3
SOT261-3
SOT261-3
SOT261-3
SOT340-1
SOT340-1
NOTE:
1. OTP = One Time Programmable EPROM.
1998 May 01
3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I
2
C, low pin count
83C751/87C751
PIN DESCRIPTIONS
PIN NO.
MNEMONIC
V
SS
V
CC
P0.0–P0.2
DIP/
SSOP
12
24
8–6
LCC
14
28
9–7
TYPE
I
I
I/O
Circuit Ground Potential
Supply voltage during normal, idle, and power-down operation.
Port 0:
Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. Port 0 also serves as the serial I
2
C
interface. When this feature is activated by software, SCL and SDA are driven low in accordance
with the I
2
C protocol. These pins are driven low if the port register bit is written with a 0 or if the I
2
C
subsystem presents a 0. The state of the pin can always be read from the port register by the
program.
To comply with the I
2
C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the
electrical characteristics listed in the tables that follow. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O in
non-I
2
C applications. Port 0 also provides alternate functions for programming the EPROM
memory as follows:
V
PP
(P0.2) –
Programming voltage input. (See Note 1.)
OE/PGM (P0.1) –
Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
ASEL (P0.0) –
Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
SDA (P0.1) –
I
2
C data.
SCL (P0.0) –
I
2
C clock.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
IL
). Port 1 serves to output the addressed EPROM contents in the verify
mode and accepts as inputs the value to program into the selected address during the program
mode. Port 1 also serves the special function features of the 80C51 family as listed below:
INT0 (P1.5):
External interrupt.
INT1 (P1.6):
External interrupt.
T0 (P1.7):
Timer 0 external input.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
IL
). Port 3 also functions as the address input for the EPROM memory location to
be programmed (or verified). The 11-bit address is multiplexed into this port as specified by
P0.0/ASEL.
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V
SS
permits a power-on RESET using only an external capacitor to
V
CC
. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and V
PP
to be applied for
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
Crystal 2:
Output from the inverting oscillator amplifier.
NAME AND FUNCTION
6
7
7
8
N/A
I
8
9
I
7
8
P1.0–P1.7
13–20
8
9
15–20,
23, 24
I/O
I/O
I/O
18
19
20
P3.0–P3.7
5–1,
23–21
20
23
24
6, 4–1,
27–25
I
I
I
I/O
RST
9
11
I
X1
11
13
I
X2
10
12
O
NOTE:
1. When P0.2 is at or close to 0V it may affect the internal ROM operation. We recommend that P0.2 be tied to V
CC
via a small pullup
(e.g., 2kΩ).
1998 May 01
5
Talking
京公网安备 11010802033920号
EEWORLD
