VersaClock
®
3S Programmable
Clock Generator
Datasheet
5L35021
Description
The 5L35021 is a member of the VersaClock 3S programmable
clock generator family with 1.8V operation voltage, and is
designed for industrial, consumer, and PCI Express applications.
The device features a 3 PLL architecture design; each PLL is
individually programmable and allowing up to 6 unique frequency
outputs.
The 5L35021 has built-in features such as Proactive Power
Saving (PPS), Performance-Power Balancing (PPB), Overshoot
Reduction Technology (ORT) and extreme low power DCO. An
internal OTP memory allows the user to store the configuration in
the device without programming after power up, then program the
5L35021 again through the I
2
C interface.
The device has programmable VCO and PLL source selection,
allowing power-performance optimization based on the application
requirements.
Features
▪
Configurable OE pin function as OE, PD#, PPS or DFC control
function
▪
Configurable PLL bandwidth; minimizes jitter peaking
▪
PPS: Proactive Power Saving features save power during the
end device power down mode
▪
PPB: Performance Power Balancing feature allows minimum
power consumption based on required performance
▪
DFC: Dynamic Frequency Control feature allows user to
dynamically switch between and up to 4 different frequencies
smoothly
▪
Spread spectrum clock to lower system EMI
▪
I
2
C interface
▪
Suspend Mode, featuring RTC clock only when system goes
into low-power operation modes
Typical Applications
▪
Embedded computing devices
▪
Consumer application crystal replacements
▪
SmartDevice, Handheld, and Consumer applications
Output Features
▪
2 DIFF outputs with configurable LPHSCL, LVCMOS output
pairs: 1MHz–250MHz (125MHz with LVCMOS mode)
▪
1 LVCMOS output: 1MHz–125MHz
▪
LVPECL, LVDS, CML and SSTL logic can be easily supported
with the LP-HCSL outputs. See application note
AN-891
for
alternate terminations
▪
Maximum of 5 LVCMOS outputs as REF + 3 × SE + 2 ×
DIFF_T/C as LVCMOS
▪
Low-power 32.768kHz clock supported for SE1 output
Key Specifications
▪
▪
▪
▪
PCIe Gen1/2/3 compliant
Typical 1.5ps rms jitter integer range: 12kHz–20MHz
Typical ultra-power-down current 50μA
< 2μA RTC clock in Suspend Mode operation
Block Diagram
CLKIN/X1
X2
Programmable
Load Capacitor
OSC
VDDDIFF 1
DIFF1
PLL1
DIFF1B
VDDDIFF 2
PLL2
Calibration
VDDSE1
VDD18
PLL3
VDDA
VBAT
32.768K
DCO
SE1
OE1
Mux
&
Divider
DIFF2
DIFF2B
SEL_DFC/ SCL_DFC1
SDA_DFC0
©2019 Integrated Device Technology, Inc.
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5L35021 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View
VDDDIFF2
17
VSSDIFF2
20
19
18
VSSDIFF1
16
15
14
VDDA
SDA_DFCO
SEL_DFC/SCL_DFC1
CLKIN/X2
CLKINB/X1
1
2
3
4
5
6
7
8
9
10
DIFF2B
DIFF2
DIFF1
DIFF1B
VDDDIFF1
OE1
SE1
5L35021
13
12
11
VBAT
VSS
3 x 3 mm 20-QFN
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
Name
V
DDA
SDA_DFC0
SEL_DFC/
SCL_DFC1
CLKIN/X2
CLKINB/X1
V
BAT
V
SS
V
DD18
V
SSSE1
V
DDSE1
SE1
OE1
V
DDDIFF1
Type
Power
I/O
Input
I/O
Input
Power
Power
Power
Power
Power
Output
Input
Power
V
DD
1.8V
VDDSE1
VSSSE1
VDD18
Description
I
2
C data pin. The pin can be DFC0 function by pin 3 SEL_DFC power-on latch status.
I
2
C CLK pin.
SEL_DFC is a latch input pin during the power-up.
High on power-on: I
2
C mode as SCLK function.
Low on power-on: pin 3 SCL and pin 2 SDA as DFC function control pins.
Crystal oscillator interface output or differential clock input pin (CLKIN).
Crystal oscillator interface input or differential clock input pin (CLKINB).
Power supply pin for 32.768kHz DCO; usually connect to coin cell battery, 1.8V.
Connect to ground.
V
DD
1.8V.
Connect to ground.
Output power supply. Connect to 1.8V. Sets output voltage levels for SE1.
Output clock SE1.
OE1’s function selected from OTP pre-programmed register bits.
OE1 pull to 6.5V when burn OTP registers.
Refer to
OE Pin Functions
table for details.
Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF1.
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5L35021 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
14
15
16
17
18
19
20
Name
DIFF1B
DIFF1
V
SSDIFF1
V
DDDIFF2
DIFF2B
DIFF2
V
SSDIFF2
EPAD
Type
Output
Output
Power
Power
Output
Output
Power
Power
Description
Differential clock output 1_Complement; can be OTP pre-programmed to
LVCMOS/LPHCSL output type.
Differential clock output 1_True; can be OTP pre-programmed to LVCMOS/LPHCSL
output type.
Connect to ground.
Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF2.
Differential clock output 2_Complement; can be OTP pre-programmed to
LVCMOS/LPHCSL output type.
Differential clock output 2_True; can be OTP pre-programmed to LVCMOS/LPHCSL
output type.
Connect to ground.
Connect to ground pad.
Detailed Block Diagram
DIV1/REF
OSC
CLKINB/X1
CLKIN/X2
PLL1
MUX
DIV
1
DIV3
DIV1/REF
DIV3
MUX
VDDDIFF2
DIFF2
DIFF2B
VDDDIFF1
DIFF1
DIFF1B
DIV
2
MUX
VBAT
VDD18
Power
Monitor
POR
MUX
PLL2
MUX
DIV
3
DIV
4
DIV
5
MUX
VDDA
VSS
Calibration
32.768K
DCO
SCL_DFC1
SDA_DFC0
I
2
C Engine
Overshot Reduction
(ORT)
MUX
PLL3
DIV4/REF
DIV5
32K
MUX
OE1
SE1
VDDSE1
Dynamic Frequency Control Logic (DFC)
OTP memory (1 configuration)
Proactive Power Saving Logic (PPS)
Timer
©2019 Integrated Device Technology, Inc.
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5L35021 Datasheet
Power Group
Table 2. Power Group
Power Supply
V
DDSE1
V
DDDIFF1
V
DDDIFF2
V
DD18
V
BAT
V
DDA
1
SE
SE1
1
DIFF
DIV
MUX
PLL
DCO
REF
Xtal
DIFF1
DIFF2
DIV3/4
DIV1
DIV5
DIV2
MUXPLL2
MUXPLL1
PLL2
PLL3
PLL1
DCO
DCO
REF
Xtal
Xtal
V
DDSE1
for non-32kHz outputs should be OFF when V
DDA
/V
DD18
turns OFF; V
BAT
mode only supports 32.768kHz outputs from SE1.
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 5L35021 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions
may affect device reliability.
Table 3. Absolute Maximum Ratings
Item
Supply Voltage, V
DDA
, V
DD18
, V
DDSE
,V
DDDIFF
Supply Voltage, V
BAT
Inputs
XIN/CLKIN
Other Inputs
Outputs, V
DDSE
x (LVCMOS)
Outputs, IO (SDA)
Package Thermal Impedance,
Θ
JA
Package Thermal Impedance,
Θ
JC
Storage Temperature, T
STG
ESD Human Body Model
Junction Temperature
V
DD
+ 5%
V
DD
+ 5%
Rating
0V to 1.8V voltage swing for both LVCMOS or DIFF CLK
-0.5V to V
DD18
or V
DDSE
x
-0.5V to V
DDSE
x or V
DDDIFF
+ 0.5V
10mA
42°C/W (0mps)
41.8°C/W (0mps)
-65°C to 150°C
2000V
125°C
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5L35021 Datasheet
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Symbol
V
DDSE
x
V
DD18
V
DDA
V
BAT
T
A
C
LOAD_OUT
F
IN
t
PU
Parameter
Power supply voltage for supporting 1.8V outputs.
Power supply voltage for core logic functions.
Analog power supply voltage. Use filtered analog power supply if
available.
Battery power supply voltage.
Operating temperature, ambient.
Maximum load capacitance (LVCMOS only).
External reference crystal.
External reference clock CLKIN, CLKINB.
Power up time for all V
DD
s to reach minimum specified voltage (power
ramps must be monotonic).
Minimum
1.71
1.71
1.71
1.71
-40
Typical
1.8
1.8
1.8
1.8
5
Maximum Units
1.89
1.89
1.89
1.89
85
40
125
3
V
V
V
V
°C
pF
MHz
ms
8
1
0.05
Crystal Characteristics
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Frequency when 32.768kHz DCO is used
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance (C
L
)
Maximum Crystal Drive Level
Conditions
—
—
—
—
—
—
—
Minimum
Typical
Maximum
Units
Fundamental
8
8
25
10
2
6
8
30
40
39
100
7
10
100
MHz
MHz
Ω
pF
pF
μW
©2019 Integrated Device Technology, Inc.
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October 4, 2019
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