21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16500T
PI74FCT162500T
Fast CMOS 18-Bit
Registered Transceivers
Product Description:
Product Features:
Common Features:5
PI74FCT16500T and PI74FCT162500T are high-speed,
low power devices with high current drive.
V
CC
= 5V ±10%
Hysteresis on all inputs
Supports Hot Insertion
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
PI74FCT16500T Features:
High output drive: I
OH
= 32 mA; I
OL
= 64 mA
Power off disable outputs permit live insertion
Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25°C
PI74FCT162500T Features:
Balanced output drivers: ±24 mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25°C
Pericom Semiconductors PI74FCT series of logic circuits are pro-
duced in the Companys advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16500T and PI74FCT162500T are 18-bit registered bus
transceivers designed with D-type latches and flip-flops to allow
data flow in transparent, latched, and clocked modes. The Output
Enable (OEAB and OEBA), Latch Enable (LEAB and LEBA) and
Clock (CLKAB and CLKBA) inputs control the data flow in each
direction. When LEAB is HIGH, the device operates in transparent
mode for A-to-B data flow. When LEAB is LOW, the A data is latched
if CLKAB is held at a HIGH or LOW logic level. The A bus data is
stored in the latch/flip-flop on the HIGH-to-LOW transition of
CLKAB, if LEAB is LOW. OEAB performs the output enable
function on the B port. Data flow from B port to A port is similar using
OEBA, LEBA and CLKBA. These high-speed, low power devices
offer a flow-through organization for ease of board layout.
The PI74FCT16500T output buffers are designed with a Power-Off
disable allowing live insertion of boards when used as backplane
drivers.
The PI74FCT162500T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
Logic Block Diagram
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
A
1
D
C
D
B
1
C
D
C
D
TO 17 OTHER CHANNELS
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PS2077A
06/27/02
Product Pin Description
Pin Name
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
GND
V
CC
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input (Active LOW)
B-to-A Clock Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Ground
Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16500/162500T
18-Bit Registered Tranceivers
Truth Table
(1,4)
OEAB
L
H
H
H
H
H
H
Inputs
LEAB
CLKAB
X
H
H
L
L
L
L
X
X
X
↓
↓
H
L
Ax
X
L
H
L
H
X
X
Outputs
Bx
Z
L
H
L
H
B
(2)
B
(3)
Product Pin Configuration
OEAB
LEAB
A
0
GND
A
1
A
2
VCC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
56-Pin
45
V, A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
0
GND
B
1
B
2
VCC
B
3
B
4
B
5
GND
B
6
B
7
B
8
B
9
B
10
B
11
GND
B
12
B
13
B
14
V
CC
B
15
B
16
GND
B
17
CLKBA
GND
NOTES:
1. A-toB data flow is shown. B-to-A data flow is similar but
uses OEBA, LEBA, and CLKBA.
2. Output level before the indicated steady-state input condi-
tions were established.
3. Output level before the indicated steady-state input condi-
tions were established, provided that CLKAB was LOW
before LEAB went LOW.
4. H = High Voltage Level
L = Low Voltage Level
Z = High Impedance
↓
= HIGH-to-LOW Transition
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PS2077A
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PI74FCT16500/162500T
18-Bit Registered Tranceivers
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................................... 65°C to +150°C
Ambient Temperature with Power Applied .................................... 40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... 0.5V to +7.0V
DC Input Voltage ............................................................................ 0.5V to +7.0V
DC Output Current ..................................................................................... 120 mA
Power Dissipation ..........................................................................................1.0W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 5.0V ± 10%)
Parameters Description
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
I
O
V
H
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
High Impedance
Output Current
Clamp Diode Voltage
Short Circuit Current
Output Drive Current
Input Hysteresis
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
CC
= Min., I
IN
= 18 mA
V
CC
= Max.
(3)
, V
OUT
= GND
V
CC
= Max.
(3)
, V
OUT
= 2.5V
Min.
2.0
V
IN
= V
CC
V
IN
= GND
V
OUT
= 2.7V
V
OUT
= 0.5V
80
50
0.7
140
100
Typ
(2)
Max.
0.8
1
1
1
1
1.2
200
180
Units
V
V
µA
µA
µA
µA
V
mA
mA
mV
PI74FCT16500T Output Drive Characteristics
(Over the Operating Range)
Parameters Description
V
OH
V
OL
I
OFF
Output HIGH Voltage
Output LOW Voltage
Power Down Disable
Test Conditions
(1)
V
CC
= Min., V
IN
= V
IH
or V
IL
V
CC
= Min., V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
OUT
≤4.5V
I
OH
= 3.0 mA
I
OH
= 15.0 mA
I
OH
= 32.0 mA
I
OL
= 64 mA
Min.
2.5
2.4
2.0
Typ
(2)
3.5
3.5
3.0
0.2
Max.
Units
V
0.55
±100
V
µA
PI74FCT162500T Output Drive Characteristics
(Over the Operating Range)
Parameters Description
V
OH
V
OL
I
ODL
I
ODH
Output HIGH Voltage
Output LOW Voltage
Output LOW Current
Output HIGH Current
Test Conditions
(1)
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OH
= 24.0 mA
V
CC
= Min., V
IN
= V
IH
or V
IL
I
OL
= 24 mA
V
CC
= 5V, V
IN
= V
IH OR
V
IL
, V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH OR
V
IL
, V
OUT
= 1.5V
(3)
Min.
2.4
60
60
Typ
(2)
3.3
0.3
115
115
Max.
0.55
150
150
Units
V
V
mA
mA
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(4)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
4.5
5.5
Max.
6
8
Units
pF
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
3
PS2077A
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PI74FCT16500/162500T
18-Bit Registered Tranceivers
Power Supply Characteristics
Parameters Description
I
CC
∆I
CC
I
CCD
Quiescent Power
Supply Current
Supply Current per
Input @ TTL HIGH
Supply Current per
Input per MHz
(4)
V
CC
= Max.
V
CC
= Max.
V
CC
= Max., Outputs Open
OEAB = OEBA = V
CC
or GND
One Bit Toggling
50% Duty Cycle
V
CC
= Max.,
Outputs Open
f
CP
= 10 MH
Z
(CLKAB)
50% Duty Cycle
OEAB = OEBA = V
CC
LEAB = GND
One Bit Toggling
f
I
= 5 MH
Z
50% Duty Cycle
V
CC
= Max., Output Open
f
CP
= 10 MH
Z
(CLKAB)
50% Duty Cycle
OEAB = OEBA = V
CC
LEAB = GND
Eighteen Bits Toggling
f
I
= 2.5 MH
Z
50% Duty Cycle
Test Conditions
(1)
V
IN
= GND or V
CC
V
IN
= 3.4V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
Typ
(2)
0.1
0.5
75
Max.
500
1.5
120
Units
µA
mA
µA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
V
IN
= GND
0.8
2.7
(5)
mA
V
IN
= 3.4V
V
IN
= GND
1.3
4.2
(5)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
3.8
7.5
(5)
8.6
21.85
(5)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
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PS2077A
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PI74FCT16500/162500T
18-Bit Registered Tranceivers
PI74FCT16500T Switching Characteristics over Operating Range
16500AT
Com.
16500CT
Com.
Min
Max
Min
16500DT
Com.
Max
Unit
Parameters
t
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
Description
CLKAB or CLKBA frequency
Propagation Delay
A
X
to B
X
or A
X
to B
X
Propagation Delay
LEBA to A
X
, LEAB to B
X
Propagation Delay
CLKBA to A
X
, CLKAB to B
X
Output Enable Time
OEBA to A
X
, OEAB to B
X
Output Disable Time
(3)
OEBA to A
X
, OEAB to B
X
Setup Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Setup Time
HIGHorLOW
Ax to LEAB,
Bx to LEBA
Clock HIGH
Clock LOW
Conditions
(1)
Min
Max
C
L
= 50 pF
R
L
= 500ohm
1.5
1.5
1.5
1.5
1.5
3.0
0
3.0
1.5
1.5
3.0
150
5.1
5.6
5.6
6.0
5.6
3.0
1.5
1.5
1.5
1.5
1.5
3.0
0
3.0
1.5
1.5
3.0
150
4.6
5.3
5.3
5.6
5.2
3.0
1.5
1.5
1.5
1.5
1.5
3.0
0
3.0
1.5
1.5
3.0
150
4.1
4.6
4.6
5.0
4.8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
H
t
W
t
W
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
LEAB or LEBA Pulse Width
HIGH
(3)
CLKAB or CLKBA Pulse Width 3.0
HIGH
(3)
or LOW
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
PS2077A
06/27/02
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