KM416RD8C/KM418RD8C
ORDERING INFORMATION
1
2
3
4
5
6
7
8
9
10
Preliminary
Direct RDRAM
™
KM 4 XX XX XX X X - X X XX
SAMSUNG Memory
Device
Organization
Product
Density
Speed
t
RAC
(Row Access Time)
Power & Refresh
Package Type
Revision
1. SAMSUNG Memory
2. Device
- 4 : DRAM
7. Package Type
- C : u - BGA(CSP-Forward)
- D : u - BGA(CSP-Reverse)
- W : WL - CSP
- S : u-BGA For Sony
3. Organization
- 16 : x16 bit
- 18 : x18 bit
8. Power & Refresh
- Blank : Normal Power Self Refesh(32m/8K, 3.9us)
-L
: Low Power Self Refesh(32m/8K, 3.9us)
-R
: Normal Power Self Refesh(32m/16K, 1.9us)
-S
: Low Power Self Refesh(32m/16K, 1.9us)
4. Product
- RD : Direct RAMBUS DRAM
5. Density
- 2 : 2M
- 4 : 4M
- 8 : 8M
- 16 : 16M
9. t
RAC
(Row Access Time)
- Blank : for Daisy Chain Sample
-G
: 53.3ns
-K
: 45ns
-M
: 40ns
- B~D, F, J, L, N~ : Reserved
6. Revision
- Blank : 1st Gen.
-A
: 2nd Gen.
10. Speed
- DS : for Daisy Chain Sample
- 60 : 600Mbps (300MHz)
- 80 : 800Mbps (400MHz)
Rev. 0.9 Apr. 1999
KM416RD8C/KM418RD8C
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 128/144-Mbit Direct Rambus DRAMs (RDRAM
®
) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz or 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's thirty-two
banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Preliminary
Direct RDRAM
™
Figure 1: Direct RDRAM CSP Package
The 128/144-Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Direct RDRAMs operate from a 2.5 volt supply.
Key Timing Parameters/Part Numbers
Speed
Organization
Binning
256Kx16x32s
a
-RG60
-RK80
-RM80
-SG60
-SK80
-SM80
256Kx18x32s
-RG60
-RK80
-RM80
-SG60
-SK80
-SM80
I/O Freq.
MHz
600
800
800
600
800
800
600
800
800
600
800
800
t
rac
(Row
Access
Time) ns
53
45
40
53
45
40
53
45
40
53
45
40
Part Number
Features
♦
Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦
Low latency features
KM416RD8C-R
b
G60
KM416RD8C-RK80
KM416RD8C-RM80
KM416RD8C-S
c
G60
KM416RD8C-SK80
KM416RD8C-SM80
KM418RD8C-RG60
KM418RD8C-RK80
KM418RD8C-RM80
KM418RD8C-SG60
KM418RD8C-SK80
KM418RD8C-SM80
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦
Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦
Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
♦
Uses Rambus Signaling Level (RSL) for up to 800MHz
a.The
“32s"designation
indicates that this RDRAM core is composed of 32
banks which use a
"split"
bank architecture.
b.The
“R"designation
indicates that this RDRAM core uses Normal Power
Self Refresh.
c.The
“S"designation
indicates that this RDRAM core uses Low Power Self
Refresh.
operation
Page 1
Rev. 0.9 Apr. 1999
KM416RD8C/KM418RD8C
Pinouts and Definitions
Forward Package
This table shows the pin assignments of the center-bonded-
forward RDRAM package from the top-side of the package
Table 1 : Forward Package (Top View)
12
11
10
9
8
7
6
5
4
3
2
1
GND
VDD
VDD
GND
SCK
VCMOS
DQA8
*
DQA6
GND
DQA3
DQA1
VDD
DQA0
VREF
GND
CTMN
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
DQB3
SIO0
VCMOS
DQB8
*
DQA7
GND
CMD
DQA4
VDD
DQA5
CFM
GND
DQA2
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB1
DQB4
VDD
DQB5
DQB7
GND
SIO1
GND
VDD
VDD
GND
Preliminary
Direct RDRAM
™
(the view looking down on the package as it is mounted on
the circuit board).
Top View
Chip
* DQA8/DQB8 are just used for
144Mb RDRAM. These two pins are
NC(No Connection) in 128Mb
RDRAM.
A
B
C
D
E
F
G
H
J
This table shows the pin assignments of the center-bonded-
Reverse RDRAM package from the top-side of the package
Table 2: Reverse Package (Top View)
12
11
10
9
8
7
6
5
4
3
2
1
GND
VDD
VDD
CMD
GND
DQA7
DQA5
VDD
DQA4
DQA2
GND
CFM
VDDa
GNDa
CFMN
RQ6
VDD
RQ5
RQ2
GND
RQ3
DQB1
VDD
DQB0
DQA8
*
VCMOS
SCK
DQA3
GND
DQA6
DQA0
VDD
DQA1
CTMN
GND
VREF
CTM
GND
RQ7
RQ4
VDD
RQ1
RQ0
GND
DQB2
GND
VDD
VDD
(the view looking down on the package as it is mounted on
the circuit board).
GND
DQB3
GND
DQB6
DQB8
*
VCMOS
SIO0
DQB5
VDD
DQB4
SIO1
GND
DQB7
GND
A
B
C
D
E
F
G
H
J
Page 2
Rev. 0.9 Apr. 1999
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
