S29CD032G0RFAI002 datasheet, PDF

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S29CD032G0RFAI002: DescriptionFlash Memory,; Categorystorage storage; File Size1MB，93 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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S29CD032G0RFAI002 Overview

Flash Memory,

S29CD032G0RFAI002 Parametric

Parameter Name	Attribute value
Maker	AMD
Reach Compliance Code	compliant

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S29CD032G

32 Megabit (1 M x 32-Bit)

CMOS 2.5 Volt-only Burst Mode, Dual Boot,

Simultaneous Read/Write Flash Memory

Data Sheet

ADVANCE

INFORMATION

Distinctive Characteristics

Architecture Advantages

Simultaneous Read/Write operations

— Data can be read from one bank while executing

erase/program functions in other bank

(-40°C to 85°C only)

— Zero latency between read and write operations

— Two bank architecture: 75%/25%

User-Defined x32 Data Bus

Dual Boot Block

— Top and bottom boot sectors in the same device

Flexible sector architecture

— Eight 8 Kbytes, sixty-two 64 Kbytes, and eight 8

Kbytes sectors

Manufactured on 170 nm process technology

SecSi (Secured Silicon) Sector (256 Bytes)

—

Factory locked and identifiable:

16 bytes for secure,

random factory Electronic Serial Number; remainder

may be customer data programmed by AMD

—

Customer lockable:

Can be read, programmed or

erased just like other sectors. Once locked, data

cannot be changed

Programmable Burst interface

— Interface to any high performance processor

— Modes of Burst Read Operation:

—

Linear Burst:

4 double words and 8 double words

with wrap around

Program Operation

— Ability to perform synchronous and asynchronous

write operations of burst configuration register

settings independently

Single power supply operation

— Optimized for 2.5 to 2.75 volt read, erase, and

program operations

Compatibility with JEDEC standards (JC42.4)

— Software compatible with single-power supply Flash

— Backward-compatible with AMD Am29LV and Am29F

flash memories

Ultra low power consumption

— Burst Mode Read: 90 mA @ 66 MHz max, capable of

75 MHz (Fortified BGA only)

— Program/Erase: 50 mA max

— Standby mode: CMOS: 60 µA max

1 million write cycles per sector typical

20 year data retention typical

VersatileI/O™ control

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V

— 1.65 V to 2.75 V compatible I/O signals

Software Features

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector (requires only V

levels)

Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-definable 64-bit password

Supports Common Flash Interface (CFI)

Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

Data# Polling and toggle bits

— Provides a software method of detecting program or

erase operation completion

Hardware Features

Program Suspend/Resume & Erase Suspend/

Resume

— Suspends program or erase operations to allow

reading, programming, or erasing in same bank

Hardware Reset (RESET#), Ready/Busy# (RY/

BY#), and Write Protect (WP#) inputs

ACC input

— Accelerates programming time for higher throughput

during system production

Package options

— 80-pin PQFP

— 80-ball Fortified BGA

Performance Characteristics

High performance read access

— Initial/random access times as fast as 48 ns

— Burst access time as fast as 7.5 ns for ball grid array

package

Publication Number

30606

Revision

Amendment

Issue Date

March 22, 2004

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by

FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

“as

is”

without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of

A d v a n c e

I n f o r m a t i o n

Table of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block Diagram of

Simultaneous Read/Write Circuit . . . . . . . . . . . . . .8

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .9

Special Package Handling Instructions .............................................10

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

x32 Mode .................................................................................................. 12

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 14

Table 1. Device Bus Operation ............................................14

Persistent Sector Protection ....................................................................................... 27

Password Sector Protection ........................................................................................ 27

WP# Hardware Protection ......................................................................................... 27

Persistent Sector Protection ............................................................ 28

Persistent Protection Bit (PPB) ..................................................................................28

Persistent Protection Bit Lock (PPB Lock) .............................................................28

Dynamic Protection Bit (DYB) ...................................................................................28

Table 11. Sector Protection Schemes .................................. 30

Persistent Sector Protection Mode Locking Bit ......................... 30

Password Protection Mode ............................................................... 30

Password and Password Mode Locking Bit ....................................31

64-bit Password ................................................................................................................ 31

VersatileI/O™ (V

) Control .............................................................. 15

Requirements for Reading Array Data ........................................... 15

Simultaneous Read/Write

Operations Overview and Restrictions .......................................... 15

Overview ............................................................................................................................ 15

Restrictions ........................................................................................................................ 15

Table 2. Bank Assignment for Boot Bank

Sector Devices .................................................................16

Write Protect (WP#) ..........................................................................32

SecSi™ (Secured Silicon) Sector Protection ..................................32

SecSi Sector Protection Bit ................................................................33

Persistent Protection Bit Lock ..........................................................33

Hardware Data Protection ................................................................33

Low V

Write Inhibit .................................................................................................. 33

Write Pulse “Glitch” Protection ................................................................................ 33

Logical Inhibit ................................................................................................................... 34

Power-Up Write Inhibit ................................................................................................ 34

and V

Power-up And Power-down Sequencing ...................................... 34

Table 12. Sector Addresses for Ordering Option 00 ............... 35

Table 13. Sector Addresses for Ordering Option 01 ............... 38

Simultaneous Read/Write Operations With Zero Latency ..... 16

Table 3. Ordering Option 00 ...............................................16

Table 4. Ordering Option 01 ...............................................16

Writing Commands/Command Sequences ................................... 16

Accelerated Program and Erase Operations .......................................................... 17

Autoselect Functions ...................................................................................................... 17

Common Flash Memory Interface (CFI) . . . . . . . .41

Table 14.

Table 15.

Table 16.

Table 17.

CFI Query Identification String ............................. 41

CFI System Interface String ................................. 42

Device Geometry Definition ................................. 43

CFI Primary Vendor-Specific Extended Query ......... 44

Automatic Sleep Mode (ASM) ........................................................... 17

Standby Mode ................................................................................................................... 17

RESET#: Hardware Reset Pin ............................................................ 18

Output Disable Mode ...........................................................................18

Autoselect Mode ................................................................................... 18

Table 5. S29CD032G Autoselect Codes (High Voltage Method) 19

Asynchronous Read Operation (Non-Burst) ................................ 19

Figure 1. Asynchronous Read Operation............................... 20

Synchronous (Burst) Read Operation ............................................ 20

Linear Burst Read Operations .......................................................... 20

Table 6. 32- Bit Linear and Burst Data Order ........................21

CE# Control in Linear Mode ...................................................................................... 22

ADV# Control In Linear Mode .................................................................................. 22

RESET# Control in Linear Mode ............................................................................... 22

OE# Control in Linear Mode ..................................................................................... 22

IND/WAIT# Operation in Linear Mode ................................................................. 22

Table 7. Valid Configuration Register Bit Definition for IND/WAIT#

Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-

Word Burst Operation........................................................ 23

Burst Access Timing Control ...................................................................................... 23

Initial Burst Access Delay Control ............................................................................ 23

Table 8. Burst Initial Access Delay .......................................24

Figure 3. Initial Burst Delay Control..................................... 24

Burst CLK Edge Data Delivery ...................................................................................24

Burst Data Hold Control ............................................................................................. 24

Asserting RESET# During A Burst Access ..............................................................24

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 46

Reading Array Data in Non-burst Mode ...................................... 46

Reading Array Data in Burst Mode ................................................ 46

Read/Reset Command .........................................................................47

Autoselect Command ..........................................................................47

Program Command Sequence ...........................................................47

Accelerated Program Command ..................................................... 48

Unlock Bypass Command Sequence .............................................. 48

Figure 4. Program Operation.............................................. 49

Unlock Bypass Entry Command .................................................................................49

Unlock Bypass Program Command ..........................................................................50

Unlock Bypass Chip Erase Command ......................................................................50

Unlock Bypass CFI Command ....................................................................................50

Unlock Bypass Reset Command ................................................................................50

Chip Erase Command ......................................................................... 50

Sector Erase Command .......................................................................51

Figure 5. Erase Operation.................................................. 52

Sector Erase and Program Suspend Command ...........................52

Sector Erase and Program Suspend Operation Mechanics ......53

Table 18. Allowed Operations During Erase/Program Suspend 53

Configuration Register ........................................................................ 25

Table 9. Configuration Register Definitions ...........................25

Table 10. Configuration Register After Device Reset ...............27

Initial Access Delay Configuration .................................................. 27

Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 27

Sector and Sector Groups ........................................................................................... 27

Sector Erase and Program Resume Command ............................54

Configuration Register Read Command ........................................54

Configuration Register Write Command ......................................54

Common Flash Interface (CFI) Command ....................................54

SecSi Sector Entry Command ............................................................55

Password Program Command ..........................................................56

Password Verify Command ................................................................56

Password Protection Mode Locking Bit Program Command .56

Persistent Sector Protection Mode Locking Bit Program Com-

30606B0 March 22, 2004

S29CD032G

A d v a n c e

I n f o r m a t i o n

mand ......................................................................................................... 57

SecSi Sector Protection Bit Program Command ........................ 57

PPB Lock Bit Set Command .............................................................. 57

DYB Write Command ........................................................................ 57

Password Unlock Command ............................................................. 58

PPB Program Command ..................................................................... 58

All PPB Erase Command .................................................................... 59

DYB Write .............................................................................................. 59

PPB Lock Bit Set .................................................................................... 59

DYB Status .............................................................................................. 59

PPB Status ............................................................................................... 59

PPB Lock Bit Status .............................................................................. 59

Non-volatile Protection Bit Program And Erase Flow ............. 59

Table 19. Memory Array Command Definitions (x32 Mode) .....61

Table 20. Sector Protection Command Definitions (x32 Mode) .62

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 10. I

CC1

Current vs. Time (Showing Active and Automatic

Sleep Currents)................................................................ 71

Figure 11. Typical I

CC1

vs. Frequency.................................. 71

Figure 12. Test Setup ....................................................... 72

Table 22. Test Specifications .............................................. 72

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Key to Switching Waveforms . . . . . . . . . . . . . . . . 72

Figure 13. Input Waveforms and Measurement Levels ........... 72

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 14. V

and V

Power-up Diagram ........................... 73

Figure 15. Conventional Read Operations Timings................. 74

Figure 16. Burst Mode Read (x32 Mode) .............................. 76

Figure 17. Asynchronous Command Write Timing ................. 77

Figure 18. Synchronous Command Write/Read Timing........... 77

Figure 19. RESET# Timings ............................................... 78

Figure 20. WP# Timing ..................................................... 79

Figure 21. Program Operation Timings ................................ 81

Figure 22. Chip/Sector Erase Operation Timings ................... 82

Figure 23. Back-to-back Cycle Timings ................................ 82

Figure 24. Data# Polling Timings

(During Embedded Algorithms) .......................................... 83

Figure 25. Toggle Bit Timings

(During Embedded Algorithms) .......................................... 83

Figure 26. DQ2 vs. DQ6 for Erase/Erase Suspend Operations . 84

Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings 84

Figure 28. Sector Protect/Unprotect Timing Diagram............. 85

Figure 29. Alternate CE# Controlled Write Operation Timings . 87

DQ7: Data# Polling .............................................................................. 63

Figure 6. Data# Polling Algorithm ....................................... 64

RY/BY#: Ready/Busy# ......................................................................... 65

DQ6: Toggle Bit I .................................................................................. 65

DQ2: Toggle Bit II ................................................................................ 66

Reading Toggle Bits DQ6/DQ2 ........................................................ 66

Figure 7. Toggle Bit Algorithm ............................................ 67

DQ5: Exceeded Timing Limits .......................................................... 68

DQ3: Sector Erase Timer ..................................................................68

Table 21. Write Operation Status ........................................68

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .69

Figure 8. Maximum Negative Overshoot Waveform................ 69

Figure 9. Maximum Positive Overshoot Waveform ................. 69

Industrial (I) Devices ......................................................................................................69

Extended (E) Devices ....................................................................................................69

Supply Voltages ......................................................................................................69

Supply Voltages .......................................................................................................69

Erase and Programming Performance . . . . . . . . 88

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 88

PQFP and Fortified BGA Pin Capacitance. . . . . 88

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 89

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . .91

March 22, 2004 30606B0

S29CD032G

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