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LMX2352TM/NOPB

Description
PLL FREQUENCY SYNTHESIZER, 1200MHz, PDSO24, PLASTIC, TSSOP-24
CategoryAnalog mixed-signal IC    The signal circuit   
File Size1MB,22 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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LMX2352TM/NOPB Overview

PLL FREQUENCY SYNTHESIZER, 1200MHz, PDSO24, PLASTIC, TSSOP-24

LMX2352TM/NOPB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
MakerRochester Electronics
Parts packaging codeTSSOP
package instructionPLASTIC, TSSOP-24
Contacts24
Reach Compliance Codeunknown
Other featuresPROVIDES 8/9 OR 16/17 PRESCALE RATIOS
Analog Integrated Circuits - Other TypesPLL FREQUENCY SYNTHESIZER
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Humidity sensitivity level1
Number of functions1
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusCOMMERCIAL
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width4.4 mm

LMX2352TM/NOPB Preview

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LMX2350/LMX2352 PLLatinum Fractional N RF / Integer N IF Dual Low Power Frequency
Synthesizer
March 2001
LMX2350/LMX2352
PLLatinum Fractional N RF / Integer N IF
Dual Low Power Frequency Synthesizer
LMX2350 2.5 GHz/550 MHz
LMX2352 1.2 GHz/550 MHz
General Description
The LMX2350/2352 is part of a family of monolithic inte-
grated fractional N/ Integer N frequency synthesizers de-
signed to be used in a local oscillator subsystem for a radio
transceiver. It is fabricated using National’s 0.5µ ABiC V
silicon BiCMOS process. The LMX2350/2352 contains dual
modulus prescalers along with modulo 15 or 16 fractional
compensation circuitry in the RF divider. A 16/17 or 32/33
prescale ratio can be selected for the LMX2350, and the
LMX2352 provides 8/9 or 16/17 prescale ratios. The IF
circuitry for both the LMX2350 and LMX2352 contains an 8/9
prescaler, and is fully programmable. Using a fractional N
phase locked loop technique, the LMX2350 /52 can gener-
ate very stable low noise control signals for UHF and VHF
voltage controlled oscillators (VCOs).
For the RF PLL, a highly flexible 16 level programmable
charge pump supplies output current magnitudes from
100µA to 1.6mA. Two uncommitted CMOS outputs can be
used to provide external control signals, or configured to
FastLock
mode. Serial data is transferred into the
LMX2350/2352 via a three wire interface (Data, LE, Clock).
Supply voltage can range from 2.7 V to 5.5 V. The LMX2350/
LMX2352 family features very low current consumption; typi-
cally LMX2350 (2.5 GHz) 6.5 mA, LMX2352 (1.2 GHz) 4.75
mA at 3.0V. The LMX2350/2352 are available in a 24-pin
TSSOP and 24-pin CSP surface mount plastic package.
Features
n
2.7 V to 5.5 V operation
n
Low current consumption
LMX2350: Icc = 6.75mA typ at 3v
LMX2352: Icc = 5.00mA typ at 3v
n
Programmable or logical power down mode
Icc = 5 µA typ at 3v
n
Modulo 15 or 16 fractional RF N divider supports ratios
of 1, 2, 3, 4, 5, 8, 15, or 16
n
Programmable charge pump current levels
RF 100µA to 1.6mA in 100µA steps
IF 100µA or 800 µA
n
Digital filtered lock detect
Applications
n
Portable wireless communications (PCS/PCN, cordless)
n
Dual mode cellular telephone systems
n
Zero blind slot TDMA systems
n
Spread spectrum communication systems (CDMA)
n
Cable TV Tuners (CATV)
Block Diagram
DS100831-1
© 2001 National Semiconductor Corporation
DS100831
www.national.com
LMX2350/LMX2352
Connection Diagrams
DS100831-2
Order Number LMX2350TM or LMX2352TM
NS Package Number MTC24
DS100831-22
Pin Descriptions
Pin No.
for CSP
Package
24
1
Pin No.
for
TSSOP
package
1
2
Pin Name
I/O
Description
OUT0
Vcc
RF
O
-
Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
RF PLL power supply voltage input. Must be equal to Vcc
IF
. May range from 2.7 V to
5.5 V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
Power supply for RF charge pump. Must be
≥V
ccRF
and V
ccIF
.
RF charge pump output. Connected to a loop filter for driving the control input of an
external VCO.
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the VCO.
RF prescaler complimentary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane.
Ground for RF PLL analog circuitry.
Dual mode oscillator output or RF R counter input. Has a Vcc/2 input threshold when
configured as an input and can be driven from an external CMOS or TTL logic gate.
Can also be configured as an output to work in conjunction with OSCin to form a
crystal oscillator. (See functional description 1.1 and programming description 3.1.)
2
3
4
5
6
7
8
3
4
5
6
7
8
9
V
pRF
CP
oRF
GND
fin RF
fin RF
GND
OSCx
-
O
-
I
I
-
I/O
www.national.com
2
LMX2350/LMX2352
Pin Descriptions
Pin No.
for CSP
Package
9
Pin No.
for
TSSOP
package
10
(Continued)
I/O
Description
Pin Name
OSCin
I
Oscillator input which can be configured to drive both the IF and RF R counter inputs
or only the IF R counter depending on the state of the OSC programming bit. (See
functional description 1.1 and programming description 3.1.)
Multiplexed output of N or R divider and RF/IF lock detect. Active High/Low CMOS
output except in analog lock detect mode. (See programming description 3.1.5.)
RF PLL Enable. Powers down RF N and R counters, prescaler, and will TRI-STATE
®
the charge pump output when LOW. Bringing RF_EN high powers up RF PLL
depending on the state of RF_CTL_WORD. (See functional description 1.9.)
IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the
charge pump output when LOW. Bringing IF_EN high powers up IF PLL depending on
the state of IF_CTL_WORD. (See functional description 1.9.)
High impedance CMOS Clock input. Data for the various counters is clocked into the
24 - bit shift register on the rising edge.
Binary serial data input. Data entered MSB first. The last two bits are the control bits.
High impedance CMOS input.
Load enable high impedance CMOS input. Data stored in the shift registers is loaded
into one of the 4 internal latches when LE goes HIGH. (See functional description 1.7.)
Ground for IF analog circuitry.
IF prescaler complimentary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane.
IF prescaler input. Small signal input from the VCO.
Ground for IF digital circuitry.
IF charge pump output. For connection to a loop filter for driving the input of an
external VCO.
Power supply for IF charge pump. Must be
V
ccRF
and V
ccIF
.
IF power supply voltage input. Must be equal to Vcc
RF
. Input may range from 2.7 V to
5.5 V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.
10
11
11
12
FoLD
RF_EN
O
I
12
13
IF_EN
I
13
14
15
16
17
18
19
20
21
22
14
15
16
17
18
19
20
21
22
23
CLOCK
DATA
LE
GND
fin IF
fin IF
GND
CPo
IF
Vp
IF
Vcc
IF
I
I
I
-
I
I
-
O
-
-
23
24
OUT1
O
3
www.national.com
LMX2350/LMX2352
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Value
Parameter
Power Supply Voltage
Symbol
Vcc
RF
Vcc
IF
Vp
RF
Vp
IF
Voltage on any pin with GND = 0 volts
Storage Temperature Range
Lead Temperature (Solder 4 sec.)
Vi
Ts
T
L
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-65
Typ
Max
6.5
6.5
6.5
6.5
Vcc + 0.3
+150
+260
Units
V
V
V
V
V
Recommended Operating Conditions
Value
Parameter
Power Supply Voltage
Symbol
Vcc
RF
Vcc
IF
Vp
RF
Vp
IF
Operating Temperature
TA
Min
2.7
Vcc
RF
Vcc
Vcc
-40
Typ
Max
5.5
Vcc
RF
5.5
5.5
+ 85
Units
V
V
V
V
C
Note 1:
“Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which the
device is intended to be functional, but do not guarantee specific perfor-
mance limits. For guaranteed specifications and test conditions, see the
Electrical Characteristics. The guaranteed specifications apply only for the
test conditions listed.
Note 2:
This Device is a high performance RF integrated circuit with an ESD
rating
<
2 KV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD-free workstations.
Electrical Characteristics
Sym-
bol
General
I
cc
Power Supply Current
Parameter
(V
ccRF
= V
ccIF
= V
PRF
= V
PIF
= 3.0V; −40˚ C
<
T
A
<
85˚ C except as specified)
Conditions
Min
Typ
Max
Units
LMX2350
LMX2352
LMX2350/52
RF and IF,
V
cc
= 2.7V to 5.5V
RF and IF,
V
cc
= 2.7V to 5.5V
IF only, V
cc
= 2.7V to 5.5V
RF_EN = IF_EN = LOW
Prescaler = 32 (Note 3)
Prescaler = 16 (Note 3)
Prescaler = 16 (Note 3)
Prescaler = 8 (Note 3)
1.2
0.5
0.5
0.25
10
No load on OSCx (Note 3)
With resonator load on
OSCx (Note 3)
2
2
6.5
4.75
1
5
8.75
6.0
2.2
20
2.5
1.2
1.2
0.5
550
50
20
10
mA
mA
mA
µA
GHz
GHz
GHz
GHz
MHz
MHz
MHz
MHz
dBm
dBm
dBm
V
PP
I
CC-PWDN
f
in
RF
Power Down Current
RF Operating
Frequency
LMX2352
LMX2350
f
in
IF
f
OSC
IF Operating Frequency
Oscillator Frequency
Pf
in RF
Pf
in IF
V
OSC
Phase Detector Frequency
RF Input Sensitivity
IF Input Sensitivity
Oscillator Sensitivity
RF and IF
2.7V≤V
CC
≤3.0V
3.0V≤V
CC
≤5.5V
2.7 V≤V
CC
5.5V
OSCin, OSCx
−15
−10
−10
0.5
0
0
0
V
CC
www.national.com
4

LMX2352TM/NOPB Related Products

LMX2352TM/NOPB LMX2352TM LMX2350SLBX
Description PLL FREQUENCY SYNTHESIZER, 1200MHz, PDSO24, PLASTIC, TSSOP-24 PLL FREQUENCY SYNTHESIZER, 1200MHz, PDSO24, PLASTIC, TSSOP-24 PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24, LAMINATE, CSP-24
Is it lead-free? Contains lead Contains lead Lead free
Maker Rochester Electronics Rochester Electronics Rochester Electronics
Parts packaging code TSSOP TSSOP QFN
package instruction PLASTIC, TSSOP-24 PLASTIC, TSSOP-24 TQCCN,
Contacts 24 24 24
Reach Compliance Code unknown unknown unknown
Other features PROVIDES 8/9 OR 16/17 PRESCALE RATIOS PROVIDES 8/9 OR 16/17 PRESCALE RATIOS SELECTABLE 16/17 OR 32/33 PRESCALE RATIO
Analog Integrated Circuits - Other Types PLL FREQUENCY SYNTHESIZER PLL FREQUENCY SYNTHESIZER PLL FREQUENCY SYNTHESIZER
JESD-30 code R-PDSO-G24 R-PDSO-G24 R-PQCC-N24
JESD-609 code e3 e0 e3
length 7.8 mm 7.8 mm 4.5 mm
Humidity sensitivity level 1 1 1
Number of functions 1 1 1
Number of terminals 24 24 24
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP TQCCN
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH CHIP CARRIER, THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 260
Certification status COMMERCIAL COMMERCIAL COMMERCIAL
Maximum seat height 1.1 mm 1.1 mm 1.2 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V
Nominal supply voltage (Vsup) 3 V 3 V 3 V
surface mount YES YES YES
technology BICMOS BICMOS BICMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface TIN TIN LEAD TIN
Terminal form GULL WING GULL WING NO LEAD
Terminal pitch 0.65 mm 0.65 mm 0.5 mm
Terminal location DUAL DUAL QUAD
Maximum time at peak reflow temperature 40 40 40
width 4.4 mm 4.4 mm 3.5 mm

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