PRELIMINARY DATASHEET
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER
ICS280
Description
The ICS280 field programmable spread spectrum clock
synthesizer generates up to four high-quality,
high-frequency clock outputs including multiple reference
clocks from a low-frequency crystal input. It is designed to
replace crystals, crystal oscillators and stand alone spread
spectrum devices in most electronic systems.
Using ICS’ VersaClock
TM
software to configure PLLs and
outputs, the ICS280 contains a One-Time Programmable
(OTP) ROM for field programmability. Programming
features include input/output frequencies, spread spectrum
amount and eight selectable configuration registers.
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
The ICS280 is also available in factory programmed custom
versions for high-volume applications.
Features
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Packaged as 16-pin TSSOP
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Configurable Spread Spectrum Modulation
Input crystal frequency of 5 to 27 MHz
Input clock frequency of 3 to 166 MHz
Up to four reference outputs
Operating voltages of 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
Available in RoHS compliant packaging
Block Diagram
VDD
PLL1 with
Spread
Spectrum
Divide
Logic
and
Output
Enable
Control
3
S2:S0
3
OTP
ROM
with PLL
Values
CLK1
PLL2
CLK2
Crystal or
Clock Input
X1/ICLK
Crystal
Oscillator
X2
External capacitors
are required with a crystal input.
CLK3
PLL3
CLK4
GND
3
PDTS
IDT™ / ICS™
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 1
ICS280
REV D 061306
ICS280
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Pin Assignment
GND
S0
S1
VDD
CLK1
CLK2
GND
X1/ICLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S2
VDD
PDTS
GND
CLK4
CLK3
VDD
X2
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
GND
S0
S1
VDD
CLK1
CLK2
GND
X1/ICLK
X2
VDD
CLK3
CLK4
GND
PDTS
VDD
S2
Pin
Type
Power
Input
Input
Power
Output
Output
Power
XI
XO
Power
Output
Output
Power
Input
Power
Input
Connect to ground.
Pin Description
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
Output clock 1. Weak internal pull-down when tri-state.
Output clock 2. Weak internal pull-down when tri-state.
Connect to ground.
Crystal input. Connect this pin to a crystal or external input clock.
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect to +3.3 V.
Output clock 3. Weak internal pull-down when tri-state.
Output clock 4. Weak internal pull-down when tri-state.
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
Connect to +3.3 V.
Select pin 2. Internal pull-up resistor.
IDT™ / ICS™
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 2
ICS280
REV D 061306
ICS280
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
External Components
The ICS280 requires a minimum number of external
components for proper operation.
The ICS280 also provides separate output divide values,
from 2 through 63, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented as:
OutputFreq
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
=
REFFreq
----
-
⋅
M
N
Output Drive Control
The ICS270 has two output drive settings. Low drive should
be selected when outputs are less than 100 MHz. High drive
should be selected when outputs are greater than 100 MHz.
(Consult the AC Electrical Characteristics for output rise and
fall times for each drive option.)
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS280
must be isolated from system power supply noise to perform
optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
ICS VersaClock Software
ICS applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Spread Spectrum Modulation
The ICS280 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electromagnetic interference (EMI). The
modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
ICS280 Configuration Capabilities
The architecture of the ICS280 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 1024 and N = 1 to 32,895.
IDT™ / ICS™
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 3
ICS280
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ICS280
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
The ICS280 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between ±0.125% to ±2.0%. For down spread,
the frequency can be modulated between -0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS280. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Junction Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD+0.5
VDD+0.5
150
260
125
Units
V
V
V
°C
°C
°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS280PG/PGLF)
Ambient Operating Temperature (ICS280PGI/PGILF)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.135
Typ.
Max.
+70
+85
Units
°C
°C
V
ms
+3.3
+3.465
4
IDT™ / ICS™
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 4
ICS280
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ICS280
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Symbol
VDD
Conditions
Config. Dependent - See
VersaClock
TM
Estimates
Min.
3.135
Typ.
Max.
3.465
Units
V
mA
Operating Supply Current
Input High Voltage
IDD
Four 33.3333 MHz outs,
VDD=3.3V;
PDTS = 1, no load, Note 1
PDTS = 0, no load
S2:S0
S2:S0
VDD-0.5
VDD/2+1
22
mA
500
0.4
0.4
Input High Voltage
Input Low Voltage
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
Input Low Voltage
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nom. Output Impedance
Internal Pull-up Resistor
Internal Pull-down
Resistor
Input Capacitance
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUS
R
PD
C
IN
µA
V
V
V
V
V
VDD/2-1
V
V
V
0.4
V
ICLK
ICLK
I
OH
= -4 mA
I
OH
= -8 mA (Low Drive);
I
OH
= -12 mA (High Drive)
I
OL
= 8 mA (Low Drive);
I
OL
= 12 mA (High Drive)
Low Drive
High Drive
S2:S0, PDTS
CLK outputs
Inputs
VDD/2+1
VDD-0.4
2.4
±40
±70
20
190
120
4
mA
Ω
kΩ
kΩ
pF
Note 1: Example with 25 MHz crystal input, four unloaded 33.3 MHz outputs.
IDT™ / ICS™
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 5
ICS280
REV D 061306
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