Intel
®
82801DBM I/O Controller
Hub 4 Mobile (ICH4-M)
Datasheet
January 200
Order Number: 252337-001
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
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whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
I/O Controller Hub 4 Mobile (ICH4-M) chipset component may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
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*Other names and brands may be claimed as the property of others.
Copyright © 2002, Intel Corporation
2
Intel
®
82801DBM ICH4-M Datasheet
Intel
®
82801DBM ICH4 Features
PCI Bus Interface
Supports PCI Revision 2.2 Specification at
33 MHz
133
MB/sec maximum throughput
Supports up to 6 master devices on PCI
One PCI REQ/GNT pair can be given higher
arbitration priority (intended for external 1394
host controller)
Support for 44-bit addressing on PCI using DAC
protocol
Integrated LAN Controller
WfM 2.0 and IEEE 802.3 compliant
LAN Connect Interface (LCI)
10/100 Mbit/sec ethernet
support
Integrated IDE Controller
Supports Native Mode register and interrupts
Independent timing of up to
4 drives, with separate
primary and secondary IDE cable connections
Ultra ATA/100/66/33, BMIDE and PIO modes
Tri-state modes to enable swap bay
USB
Includes 3 UHCI host controllers that support 6
external ports
New: Includes 1 EHCI high-speed USB 2.0 Host
Controller that supports all six ports
New: Supports a USB 2.0 high-speed debug port
Supports wake-up from sleeping states S1-MS5
Supports legacy keyboard/mouse software
AC'97 Link for Audio and Telephony CODECs
New: Third AC_SDATA_IN
line for three codec
support
Supports AC 97 2.3
New: Independent bus master logic for 7 channels
(PCM In/Out, Mic 1 input, Mic 2 input, modem
in/out, S/PDIF out)
Separate independent PCI
functions for audio and
modem
Support for up to six channels of PCM audio
output (full AC3 decode)
Supports wake-up events
Interrupt Controller
Support up to 8 PCI interrupt pins
Supports PCI 2.2 message signaled interrupts
Two cascaded 82C59
with 15 interrupts
Integrated I/O APIC capability
with 24 interrupts
Supports serial interrupt protocol
Supports processor system bus interrupt delivery
New: 1.5 V operation with 3.3 V I/O
5V tolerant buffers on IDE, PCI, USB over-current
and legacy signals
Timers Based on 82C54
System timer, refresh request, speaker tone output
Power Management Logic
ACPI 2.0 compliant
ACPI-defined power states (C1C4, S1-M,
S3S5)
ACPI power management timer
Support for Intel
®
SpeedStep
TM
technology
processor power control
(Support for Deeper Sleep power state
PCI CLKRUN# and PME# support
SMI# generation
All registers readable/restorable
for proper resume
from 0 V suspend states
External Glue Integration
Integrated pull-up, pull-down and series
termination resistors on IDE, processor interface
Integrated Pull-down and Series resistors on USB
Enhanced Hub Interface buffers improve routing
flexibility (Not available with all Memory Controller
Hubs)
Firmware Hub (FWH) Interface supports BIOS
memory size up to 8 MB
Low Pin Count (LPC) Interface
Supports two Master/DMA devices.
Enhanced DMA Controller
Two cascaded 8237 DMA controllers
PCI DMA: Supports PC/PCI Includes two
PC/PCI REQ#/GNT# pairs
Supports LPC DMA
Supports DMA collection buffer to provide
Type-F DMA performance for all DMA channels
Real-Time Clock
256-byte battery-backed CMOS RAM
System TCO Reduction Circuits
Timers to generate SMI# and Reset upon detection
of system hang
Timers to detect improper processor reset
Supports ability to disable external devices
SMBus
New: Hardware packet error checking
New: Supports SMBus 2.0 Specification
Host interface allows processor to communicate
via SMBus
Slave interface allows an
external microcontroller
to access system resources
Compatible with most 2-wire components that are
also I
2
C compatible
GPIO
TTL, open-drain, inversion
Package 31x31 mm 421 BGA
The Intel
®
82801DBM ICH4-M may contain design defects or errors known as errata which may cause the products to deviate
from published specifications. Current characterized errata are available on request.
Intel
®
82801DBM ICH4-M Datasheet
3
System Configuration
Processor
AGP
Host Controller
Memory
USB
(Supports 6
USB 2.0 ports)
IDE-Primary
IDE-Secondary
AC97 Codec(s)
LAN Connect
GPIO
Firmware Hub(s)
Firmware Hubs
(1-8)
Othe ASIC
Other ASICs
r
s
(Optional)
LPC Interface
Super I/O
Super I/O
Intel
®
82801DBM
ICH4-M
Power Management
Clock Generators
Clock Generators
System Management (TCO)
SMBus/I
2
C
PCI Bus
Docking
Bridge
Cardbus Controller
(and Attached Slots)
SysBlk_ICH4-M
4
Intel
®
82801DBM ICH4-M Datasheet
Contents
1
Introduction
...........................................................................................................33
1.1
1.2
About This Datasheet .................................................................................... 33
Overview ........................................................................................................ 36
Hub Interface to Host Controller .................................................................... 45
Link to LAN Connect ......................................................................................45
EEPROM Interface ........................................................................................46
Firmware Hub Interface ................................................................................. 46
PCI Interface .................................................................................................. 46
IDE Interface .................................................................................................. 49
LPC Interface ................................................................................................. 50
Interrupt Interface........................................................................................... 50
USB Interface................................................................................................. 51
Power Management Interface........................................................................52
Processor Interface........................................................................................ 54
SMBus Interface ............................................................................................ 55
System Management Interface ...................................................................... 55
Real Time Clock Interface.............................................................................. 56
Other Clocks .................................................................................................. 56
Miscellaneous Signals ................................................................................... 56
AC97 Link......................................................................................................57
General Purpose I/O ...................................................................................... 58
Power and Ground ......................................................................................... 59
Pin Straps ...................................................................................................... 60
2.20.1 Functional Straps .............................................................................. 60
2.20.2 External RTC Circuitry ...................................................................... 61
2.20.3 V5REF / Vcc3_3 Sequencing Requirements .................................... 61
2.20.4 Test Signals ......................................................................................62
2.20.4.1 Test Mode Selection.......................................................... 62
Power Planes.................................................................................................63
Integrated Pull-Ups and Pull-Downs .............................................................. 64
IDE Integrated Series Termination Resistors................................................. 64
Output and I/O Signals Planes and States .................................................... 65
Power Planes for Input Signals...................................................................... 69
2
Signal Description
..............................................................................................43
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
3
Intel
®
ICH4-M Power Planes and Pin States
............................................63
3.1
3.2
3.3
3.4
3.5
4
5
Intel
®
ICH4-M System Clock Domains
........................................................71
Functional Description
.....................................................................................73
5.1
Hub Interface to PCI Bridge (D30:F0) ............................................................ 73
5.1.1 PCI Bus Interface .............................................................................. 73
5.1.2 PCI-to-PCI Bridge Model .................................................................. 74
5.1.3 IDSEL to Device Number Mapping ................................................... 74
5.1.4 SERR# Functionality......................................................................... 74
5.1.5 Parity Error Detection........................................................................ 76
5.1.6 Standard PCI Bus Configuration Mechanism ................................... 77
Intel
®
82801DBM ICH4-M Datasheet
5
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