iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
32Mx72 DDR SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR SDRAM Data Rate = 200, 250, 266, 333Mbps
Package:
•
208 Plastic Ball Grid Array (PBGA), 16 x 23mm-1.0mm pitch
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Industrial, Enhanced and Military Temperature
Ranges
Organized as 32M x 72/80
Weight: AS4DDR32M72PBG </= 2.0 grams typical
* This product and or it’s specifications is subject to change without notice.
BENEFITS
40 - 70% SPACE SAVINGS
Reduced part count
Reduced I/O count
•
34% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
PIN/Function compatible to White
W3E32M72S-xSBx
Configuration Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
32 Meg x 72
8 Meg x 16 x 4 Banks
8K
8K (A0 A12)
4 (BA0 BA1)
1K (A0 A9)
FUNCTIONAL BLOCK DIAGRAM
CLK0
CLK0\
CKE0
CS0
WE0\
RAS0\
CAS0\
DQML0
DQMH 0
DQSL0
DQSH 0
VRef
VCC
VCCQ
VSS
Ax,BA0-1
CLK2
CLK2\
CKE2
CS2
WE2\
RAS2\
CAS2\
DQML2
DQMH 2
DQSL2
DQSH 2
SD R AM
DDR
x16
2. 5V Cor e
2.5V I /O
SD R AM
DDR
x16
2.5V Cor e
2. 5V I/ O
CLK1
CLK1\
CKE1
DQ0-15 CS0
WE1\
RAS1\
CAS1\
DQML1
DQMH 1
DQSL1
DQSH 1
CLK4
CLK4\
SD R AM
DDR
x16
2. 5V Cor e
2.5V I /O
CKE4
CS4
DQ16-31
WE4\
RAS4\
CAS4\
DQML4
DQMH 4
DQSL4
DQSH 4
SD R AM
DDR
x16
2. 5V Cor e
2.5V I /O
DQ64-79
CLK3
CLK3\
CKE3
DQ32-47 CS3
WE3\
RAS3\
CAS3\
DQML3
DQMH 3
DQSL3
DQSH 3
SD R AM
DDR
x16
2.5V Cor e
2. 5V I/ O
DQ48-63
AS4DDR32M72PBG1
Rev. 0.2 06/09
Micross Componentsreserves the right to change products or specifications without notice.
1
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
SDRAM-DDR Pinout Top View
Rev. A, 12/07, 208BGA-1.00MM PITCH - X72
1
A
B
C
VCCQ
VSS
2
VCC
VSS
CK0\
3
VSS
CS2\
CK2\
4
VCCQ
CS0\
CK0
5
VCCQ
CKE2
CK2
DQ8
DQ43
DQ14
DQ48
DQ67
VCC
VSS
VCCQ
DQ68
DQ48
DQ17
DQ51
DQ20
6
VSS
CKE0
7
VCCQ
CAS2\
8
VCCQ
RAS0\
CAS0\
DQ39
DQ36
DQ34
DQ0
DQ73
A7
VCCQ
A6
9
VSS
RAS2\
WE0\
DQ7
DQ4
DQ2
DQ77
DQ74
A9
A4
A8
CK4\
DQ62
DQ29
DQ26
10
VCC
VSS
WE2\
DQSL2
DQ38
DQ37
DQ79
DQ75
DNU
A11
A5
CK4
CKE4
DQ59
DQ57
11
VSS
A
VCCQ B
VSS
C
DQML0 DQML2
DQ40
DQ12
DQ33
VSS
VCC
VSS
VREF
VSS
VCC
VSS
DQ49
DQ60
DQ56
DQ5
DQ3
DQ1
DQ32
DQ72
VCCQ
VSS
VCC
D
DQMH2 DQMH0 DQSH2 DQSH0
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQ41
DQ44
DQ64
DNU
VCCQ
VSS
VCC
DQ71
WE4\
DQ22
DQ23
DQSL1
VSS
VCCQ
VSS
1
DQ9
DQ11
DQ65
DQ66
A12
A10
A2
DQ70
CAS4\
DQ52
DQ54
DQSL3
CAS3\
VSS
VCC
2
DQ10
DQ13
DQ15
DQ69
BA1
A3
BA0
DQ42
DQ45
DQ47
DNU
A0
VCCQ
A1
DQSL0
D
DQ6
DQ36
E
F
DQ78
G
DQ76
H
VCC
VSS
J
K
VCCQ L
DNU
CS4\
DQ27
DQ25
M
N
p
R
DQSL4 DQML4
RAS4\
DQ18
DQ21
DQ55
WE3\
CAS1\
VSS
3
DQ16
DQ50
DQ19
DQ53
WE1\
RAS3\
VCCQ
4
DQSH4 DQMH4
DQ63
DQ30
DQ28
DQ24
CK1\
CKE3
VCCQ
7
DQ31
DQ61
DQ58
DQMH3 DQMH1 DQSH1 DQSH3
T
CK3\
CS1\
VCCQ
8
CK1
CS3\
VSS
9
CK3
VSS
VCC
10
VSS
U
DQML3 DQML1
RAS1\
VCCQ
5
CKE1
VSS
6
VCCQ V
VSS
11
W
Ground
CNTRL
Data I/O
Array Power
I/O Power
Level REF.
UNPOPULATED
NC
Address
DNU
AS4DDR32M72PBG1
Rev. 0.2 06/09
Micross Componentsreserves the right to change products or specifications without notice.
2
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
PIN DEFINITIONS / FUNCTIONAL DESCRIPTION
BGA Location
B5,B6,N10,V6,V7
C4,C5,M10,U9,U10
C2,C3,M9,U7,U8
B3,B4,N11,V8,V9
B7,C8,N2,U2,V3
B8,B9,N4,V4,V5
C9,C10,N1U3,U4
C6,C7M4,U5,U6
D1,D2,M8,T8,T9
D10,D11M3,T1,T2
D3,D4M7,T10,T11
J4,L4,L2,K3,K9,L10,
L8,J8,L9,J9,K2,K10,
J2
L3, J3
H1,H3,J10,M11
D5,D6,D7,D8,D9,E1,E2,
E3,E4,E5,E6,E7,E8,E9,
E10,E11,F1,F2,F3,F4,
F5,F6,F7,F8,F9,F10,
G1,G2,G3,G4,G5,G7,
G8,G9,G10,G11,H2,H3,
H5,H7,H8,H9,H10,H11,
M1,M2,M5,N4,N5,N7,N8,
N9,P1,P2,P3,P4,P5,P6,
P7,P8,P9,P10,P11,R1,
R2,R3,R4,R5,R6,R7,R8,
R9,R10,R11,T3,T4,T5,
T6,T7,
T6 T7
K6
A2,A10,H6,J5,J11,L1,
L7,M6,W2,W10
A4,A5,A7,A8,B1,B2,J1,
J7,K4,K8,L5,L11,V1,
V11,W4,W5,W7,W8
A3,A6,A9,A11,B2,B10,
C1,C11,G6,J6,K1,K5,
K7,K11,L6,N6,U1,U11,
V2,V10,W1,W3,W6,W9,
W11
Symbol
CKEx
CKx
CKx\
CSx\
CASx\
RASx\
WEx\
DQMLx
DQMHx
DQSLx
DQSHx
Ax
BAx
DNU
Type
Description
Clock Enable, enabler of all on silicon clock circuitry
Clock input (active HIGH) part of a differential pair (1 pair per x16 bits)
Clock input (active LOW) part of a differential pair (1pair per x16 bits)
Chip Selects, one per x16 bits (active LOW)
Column Address Select (1 per x16 bits)
Row Address Select (1 per x16 bits)
WRITE enable input (active LOW, 1 per x16 bits)
CNTL Input
Array Address input providing ROW addresses for ACTIVE commands and
ADDR Input the COLUMN address and AUTO PRECHARGE bit (A10) for READ/WRITE
commands
Input
Bank Address select input
Future Use
DQx
Input/Output Data, bi-directional Input/Output pins
Vref
VCC
VCCQ
Supply
Supply
Supply
SSTL-25 Voltage Reference
Core Power Supply
IO Power Supply
VSS
Supply
Ground Return
UNPOPULATED
Unpopulated ball matrix location (location registration aid)
AS4DDR32M72PBG1
Rev. 0.2 06/09
Micross Componentsreserves the right to change products or specifications without notice.
3
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
GENERAL DESCRIPTION
The 2.4Gb DDR SDRAM MCM, is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a quad-
bank DRAM. Each of the chip’s 134,217,728-bit banks
is organized as 8,192 rows by 1024 columns by 32 bits.
The 256MB(2.4Gb) DDR SDRAM MCM uses a DDR
architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n-prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 256MB DDR SDRAM effectively consists of a single 2n-bit
wide, one-clock-cycle data tansfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs and
by the memory contoller during WRITEs. DQS is edgealigned
with data for READs and center-aligned with data for WRITEs.
Each chip has two data strobes, one for the lower byte and
one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CLK and CLK#); the crossing of CLK going HIGH and CLK#
going LOW will be referred to as the positive edge of CLK.
Commands (address and control signals) are registered at
every positive edge of CLK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or WRITE
command are used to select the bank and the starting column
location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge function
may be enabled to provide a selftimed row precharge that is
initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a powersaving
power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0-12 select the row). The address bits
registered coincident with the READ or WRITE command
are used to select the starting column location for the burst
access.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register defi nition, command descriptions and
device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those
specified may result in undefined operation. Power must
fi
rst
be applied to V
CC
and V
CCQ
simultaneously, and then to V
REF
(and to the system V
TT
). V
TT
must be applied after V
CCQ
to avoid
device latch-up, which may cause permanent damage to the
device. V
REF
can be applied any time after V
CCQ
but is expected
to be nominally coincident with V
TT
. Except for CKE, inputs are
not recognized as valid until after V
REF
is applied. CKE is an
SSTL_2 input but will detect an LVCMOS LOW level after V
CC
is applied. Maintaining an LVCMOS LOW level on CKE during
powerup is required to ensure that the DQ and DQS outputs
will be in the High-Z state, where they will remain until driven in
normal operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200μs delay prior to applying an executable
command.
Once the 200μs delay has been satisfied, a DESELECT or NOP
command should be applied, and CKE should be brought HIGH.
Following the NOP command, a PRECHARGE ALL command
should be applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1 LOW
and BA0 HIGH) to enable the DLL, followed by another LOAD
MODE REGISTER command to the mode register (BA0/ BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required between
the DLL reset and any READ command. A PRECHARGE ALL
command should then be applied, placing the device in the all
banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed (t
RFC
must be satisfi ed.) Additionally, a LOAD MODE
REGISTER command for the mode register with the reset DLL
bit deactivated (i.e., to program operating parameters without
resetting the DLL) is required. Following
these requirements, the DDR SDRAM is ready for normal
operation.
Micross Componentsreserves the right to change products or specifications without notice.
AS4DDR32M72PBG1
Rev. 0.2 06/09
4
iPEM
2.4Gb SDRAM-DDR
AS4DDR32M72PBG1
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and
an operating mode, as shown in Figure 3. The Mode Register
is programmed via the MODE REGISTER SET command (with
BA0 = 0 and BA1 = 0) and will retain the stored information until
it is programmed again or the device loses power. (Except for
bit A8 which is self clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are idle
and no bursts are in progress, and the controller must wait
the specified time before initiating the subsequent operation.
Violating either of these requirements will result in unspecified
operation. Mode register bits A0-A2 specify the burst length,
A3 specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A12 specify the operating
mode.
TABLE 1 - BURST DEFINITION
Burst
Length
2
Starting Column
Address
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
4
8
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum number
of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4 or 8 locations
are available for both the sequential and the interleaved burst
types.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is reached.
The block is uniquely selected by A1-Ai when the burst length
is set to two; by A2-Ai when the burst length is set to four
(where Ai is the most significant column address for a given
configuration); and by A3-Ai when the burst length is set to eight.
The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. The programmed
burst length applies to both READ and WRITE bursts.
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block;
A0 selects the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block;
A0-1 select the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
READ LATENCY
The READ latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
fi
rst
bit of output data. The latency can be set to 2 or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at which
each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
CAS
LATENCY=2 LATENCY=2.5
75
100
100
125
100
133
100
166
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type
and is selected via bit M3. The ordering of accesses within a
burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 1.
SPEED
-10
-8
-75
-6
AS4DDR32M72PBG1
Rev. 0.2 06/09
Micross Componentsreserves the right to change products or specifications without notice.
5
京公网安备 11010802033920号
EEWORLD
