TSXPC603RMGU14LC datasheet, PDF

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TSXPC603RMGU14LC: DescriptionRISC Microprocessor, 32-Bit, 300MHz, CMOS, CBGA255, 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255; CategoryThe embedded processor and controller Microcontrollers and processors; File Size791KB，57 Pages; Manufacturere2v technologies

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TSXPC603RMGU14LC Overview

RISC Microprocessor, 32-Bit, 300MHz, CMOS, CBGA255, 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255

TSXPC603RMGU14LC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA,
Contacts	255
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	75 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B255
JESD-609 code	e0
length	21 mm
low power mode	YES
Number of terminals	255
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3 mm
speed	300 MHz
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	21 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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TSPC603R

PowerPC 603e RISC Microprocessor

Family PID7t-603e

Datasheet

Features

•

Superscalar (3 Instructions per Clock Peak)

Dual 16 KB Caches

Selectable Bus Clock

32-bit Compatibility PowerPC Implementation

On-chip Debug Support

Nap, Doze and Sleep Power Saving Modes

Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255

Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255

•

7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)

Typically = 3.5W (266 MHz), Full Operating Conditions

Branch Folding

64-bit Data Bus (32-bit Data Bus Option)

4-Gbytes Direct Addressing Range

Pipelined Single/Double Precision Float Unit

IEEE 754 Compatible FPU

IEEE P 1149-1 Test Mode (JTAG/C0P)

INT

Max = 300 MHz

BUS

Max = 75 MHz

Compatible CMOS Input/TTL Output

Features Specific to Cerquad

•

5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)

•

Typically = 2.5W (200 MHz), Full Operating Conditions

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2007

0841C–HIREL–06/07

TSPC603R

1. Description

The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power imple-

mentation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family. The 603R

is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements

32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and

64 bits.

The 603R is a low-power 2.5/3.3V design and provides four software controllable power-saving modes.

This device is a superscalar processor capable of issuing and retiring as many as three instructions per

clock. Instructions can be executed in any order for increased performance, but, the 603R makes com-

pletion appear sequential. It integrates five execution units and is able to execute five instructions in

parallel.

The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed

caches for instructions and data, as well as on-chip instructions, and data Memory Management Units

(MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation look

aside buffers that provide support for demand-paged virtual memory address translation and vari-

able-sized block translation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus.

The interface protocol allows multiple masters to compete for system resources through a central exter-

nal arbiter. The device supports single-beat and burst data transfers for memory accesses, and supports

memory-mapped I/Os.

The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface compati-

bility with TTL devices. It also integrates in-system testability and debugging features through JTAG

boundary-scan capabilities.

2. Screening/Quality/Packaging

This product is manufactured in full compliance with:

• HiTCE CBGA according to e2v Standards

• CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to e2v standards

• CBGA 255: Upscreenings based upon e2v standards

• CBGA, CI-CGA, HiTCE packages:

– Full military temperature range (T

= -55°C, T

= +125°C)

– Industrial temperature range

• Cerquad:

– Full military temperature range (T

= -55°C, T

= +125°C)

– Industrial temperature range

= -40°C, T

= +110°C)

– Commercial temperature ranges (

= 0°C,

= +70°C)

• Internal I/O Power Supply = 2.5 ±5% // 3.3V ±5%

= -40°C, T

= +110°C)

0841C–HIREL–06/07

e2v semiconductors SAS 2007

TSPC603R

• a Branch Processing Unit (BPU)

• a Load/Store Unit (LSU)

• a System Register Unit (SRU)

The ability to execute five instructions in parallel and the use of simple instructions with rapid execution

times yield high efficiency and throughput for 603R-based systems. Most integer instructions execute in

one clock cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every

clock cycle.

The 603R provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed

caches for instructions and data, as well as on-chip instruction and data Memory Management Units

(MMUs). The MMUs contain 64-entry, two-way set-associative, Data and Instruction Translation Looka-

side Buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation

and variable-sized block translation. The TLBs and caches use a Least Recently Used (LRU) replace-

ment algorithm. The 603R also supports block address translation through the use of two independent

Instruction and Data Block Address Translation (IBAT and DBAT) arrays of four entries each. Effective

addresses are compared simultaneously with all four entries in the BAT array during block translation. In

accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array,

the BAT translation has priority.

The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603R interface protocol

allows multiple masters to compete for system resources through a central external arbiter. The 603R

provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache

states. This protocol is a compatible subset of the MESI (Modified/Exclusive/Shared/Invalid) four-state

protocol and operates coherently in systems that contain four-state caches. The 603R supports sin-

gle-beat and burst data transfers for memory accesses, and supports memory-mapped I/Os.

The 603R uses an advanced, 0.29 µm 5-metal-layer CMOS process technology and maintains full inter-

face compatibility with TTL devices.

5. Signal Description

Figure 5-1 on page 5, Table 10-5

and

Table 10-6 on page 20

describe the signals on the TSPC603R and

indicate signal functions. The test signals, TRST, TMS, TCK, TDI and TDO, comply with the subset

P-1149.1 of the IEEE testability bus standard.

The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use only and

must be pulled up to V

for normal machine operations.

0841C–HIREL–06/07

e2v semiconductors SAS 2007

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