Classic
®
EPLD Family
Data Sheet
May 1999, ver. 5
Features
s
s
s
s
s
s
s
s
s
s
Complete device family with logic densities of 300 to 900 usable gates
(see
Table 1)
Device erasure and reprogramming with non-volatile EPROM
configuration elements
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
Programmable security bit for protection of proprietary designs
100% generically tested to provide 100% programming yield
Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
Software design support featuring the Altera
®
MAX+PLUS
®
II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
Usable gates
Macrocells
Maximum user I/O pins
t
PD
(ns)
f
CNT
(MHz)
EP610
EP610I
300
16
22
10
100
EP910
EP910I
450
24
38
12
76.9
EP1810
900
48
64
20
50
Altera Corporation
A-DS-CLASSIC-05
745
Classic EPLD Family Data Sheet
General
Description
The Altera Classic
TM
device family offers a solution to high-speed, low-
power logic integration. Fabricated on advanced CMOS technology,
Classic devices also have a Turbo-only version, which is described in this
data sheet.
Classic devices support 100% TTL emulation and can easily integrate
multiple PAL- and GAL-type devices with densities ranging from 300 to
900 usable gates. The Classic family provides pin-to-pin logic delays as
low as 10 ns and counter frequencies as high as 100 MHz. Classic devices
are available in a wide range of packages, including ceramic dual in-line
package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip
carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA),
and small-outline integrated circuit (SOIC) packages.
EPROM-based Classic devices can reduce active power consumption
without sacrificing performance. This reduced power consumption
makes the Classic family well suited for a wide range of low-power
applications.
Classic devices are 100% generically tested devices in windowed
packages and can be erased with ultra-violet (UV) light, allowing design
changes to be implemented quickly.
Classic devices use sum-of-products logic and a programmable register.
The sum-of-products logic provides a programmable-AND/fixed-OR
structure that can implement logic with up to eight product terms. The
programmable register can be individually programmed for D, T, SR, or
JK flipflop operation or can be bypassed for combinatorial operation. In
addition, macrocell registers can be individually clocked either by a global
clock or by any input or feedback path to the
AND
array. Altera’s
proprietary programmable I/O architecture allows the designer to
program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to implement a variety of logic functions simultaneously.
Classic devices are supported by Altera’s MAX+PLUS II development
system, a single, integrated package that offers schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The
MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL,
Verilog HDL, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and workstation-
based EDA tools. The MAX+PLUS II software runs on Windows-based
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations. These devices also contain on-board logic test
circuitry to allow verification of function and AC specifications during
standard production flow.
746
Altera Corporation
Classic EPLD Family Data Sheet
f
Functional
Description
For more information, see the
MAX+PLUS II Programmable Logic
Development System & Software Data Sheet.
The Classic architecture includes the following elements:
s
s
s
s
Macrocells
Programmable registers
Output enable/clock select
Feedback select
Macrocells
Classic macrocells, shown in
Figure 1,
can be individually configured for
both sequential and combinatorial logic operation. Eight product terms
form a programmable-AND array that feeds an
OR
gate for combinatorial
logic implementation. An additional product term is used for
asynchronous clear control of the internal register; another product term
implements either an output enable or a logic-array-generated clock.
Inputs to the programmable-AND array come from both the true and
complement signals of the dedicated inputs, feedbacks from I/O pins that
are configured as inputs, and feedbacks from macrocell outputs. Signals
from dedicated inputs are globally routed and can feed the inputs of all
device macrocells. The feedback multiplexer controls the routing of
feedback signals from macrocells and from I/O pins. For additional
information on feedback select configurations, see
Figure 3 on page 749.
Figure 1. Classic Device Macrocell
Logic Array
Global
Clock
VCC
Output Enable/Clock Select
OE
CLK
Q
CLR
Programmable
Register
Input, I/O, and
Macrocell
Feedbacks
To Logic Array
Feedback
Select
Asynchronous Clear
Altera Corporation
747
Classic EPLD Family Data Sheet
The eight product terms of the programmable-AND array feed the 8-input
OR
gate, which then feeds one input to an
XOR
gate. The other input to the
XOR
gate is connected to a programmable bit that allows the array output
to be inverted. Altera’s MAX+PLUS II software uses the
XOR
gate to
implement either active-high or active-low logic, or De Morgan’s
inversion to reduce the number of product terms needed to implement a
function.
Programmable Registers
To implement registered functions, each macrocell register can be
individually programmed for D, T, JK, or SR operation. If necessary, the
register can be bypassed for combinatorial operation. During design
compilation, the MAX+PLUS II software selects the most efficient register
operation for each registered function to minimize the logic resources
needed by the design. Registers have an individual asynchronous clear
function that is controlled by a dedicated product term. These registers
are cleared automatically during power-up.
In addition, macrocell registers can be individually clocked by either a
global clock or any input or feedback path to the
AND
array. Altera’s
proprietary programmable I/O architecture allows the designer to
program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to simultaneously implement a variety of logic functions.
Output Enable/Clock Select
Figure 2
shows the two operating modes (Modes 0 and 1) provided by the
output enable/clock (OE/CLK) select. The
OE/CLK
select, which is
controlled by a single programmable bit, can be individually configured
for each macrocell. In Mode 0, the tri-state output buffer is controlled by
a single product term. If the output enable is high, the output buffer is
enabled. If the output enable is low, the output has a high-impedance
value. In Mode 0, the macrocell flipflop is clocked by its global clock input
signal.
In Mode 1, the output enable buffer is always enabled, and the macrocell
register can be triggered by an array clock signal generated by a product
term. This mode allows registers to be individually clocked by any signal
on the
AND
array. With both true and complement signals in the
AND
array,
the register can be configured to trigger on a rising or falling edge. This
product-term-controlled clock configuration also supports gated clock
structures.
748
Altera Corporation
Classic EPLD Family Data Sheet
Figure 2. Classic Output Enable/Clock Select
Mode 0
Global
Clock
AND
Array
CLK
VCC
OE
Output Enable/Clock
Select
In Mode 0, the register
is clocked by the global
clock signal. The
output is enabled by
the logic from the
product term.
Data
Q
OE = Product Term
CLK = Global
CLR
Macrocell
Output Buffer
Mode 1
Global
Clock
VCC
OE
Output Enable/Clock
Select
In Mode 1, the output
AND
is permanently enabled
Array
and the register is
clocked by the product
term, which allows
gated clocks to be
generated.
OE = Enabled
CLK = Product Term
CLK
Data
Q
CLR
Macrocell
Output Buffer
Feedback Select
Each macrocell in a Classic device provides feedback selection that is
controlled by the feedback multiplexer. This feedback selection allows the
designer to feed either the macrocell output or the I/O pin input
associated with the macrocell back into the
AND
array. The macrocell
output can be either the
Q
output of the programmable register or the
combinatorial output of the macrocell. Different devices have different
feedback multiplexer configurations. See
Figure 3.
Figure 3. Classic Feedback Multiplexer Configurations
Global Feedback Multiplexer
Global
EP610
EP610I
EP910
EP910I
Q
I/O
Quadrant Feedback Multiplexer
Quadrant
EP1810
Q
I/O
Dual Feedback Multiplexer
Quadrant
Global
EP1810
Q
I/O
Altera Corporation
749
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