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IDT70927S20G

Description
Dual-Port SRAM, 32KX16, 20ns, CMOS, CPGA108, PGA-108
Categorystorage    storage   
File Size193KB,15 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

IDT70927S20G Overview

Dual-Port SRAM, 32KX16, 20ns, CMOS, CPGA108, PGA-108

IDT70927S20G Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instructionPGA, PGA108,12X12
Contacts108
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.B
Maximum access time20 ns
I/O typeCOMMON
JESD-30 codeS-CPGA-P108
JESD-609 codee0
length30.48 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Number of functions1
Number of ports2
Number of terminals108
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX16
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA108,12X12
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum standby current0.015 A
Minimum standby current4.5 V
Maximum slew rate0.39 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width30.48 mm
HIGH-SPEED 32K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features
x
x
PRELIMINARY
IDT70927S/L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 20/25/30ns
Low-power operation
– IDT70927S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT70927L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
x
x
x
x
x
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 20ns clock to data out
– Self-timed write allows fast cycle time
– 25ns cycle time, 40MHz operation
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 108-pin Pin Grid Array (PGA) and 100 pin Thin
Quad Flatpack (TQFP) packages
Functional Block Diagram
R/W
L
UB
L
CE
0L
CE
1L
LB
L
OE
L
R/W
R
UB
R
CE
0R
CE
1R
LB
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
I/O
Control
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
A
14L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
14R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3201 drw 01
JUNE 1999
1
©1999 Integrated Device Technology, Inc.
DSC-3201/7
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