AT49BV801T-90CI datasheet, PDF

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AT49BV801T-90CI: DescriptionFlash, 512KX16, 90ns, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CSBGA-48; Categorystorage storage; File Size235KB，27 Pages; ManufacturerAtmel (Microchip)

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AT49BV801T-90CI Overview

Flash, 512KX16, 90ns, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CSBGA-48

AT49BV801T-90CI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	6 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CSBGA-48
Contacts	48
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	90 ns
Spare memory width	8
startup block	TOP
command user interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B48
JESD-609 code	e0
length	8 mm
memory density	8388608 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	8,15
Number of terminals	48
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA48,6X8,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	8K,64K
Maximum standby current	0.00001 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.65 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	6 mm

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Features

•

Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)

•

Access Time – 70 ns

•

Sector Erase Architecture

•

– Fifteen 32K Word (64K Bytes) Sectors with Individual Write Lockout

– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

Fast Word Program Time – 20 µs

Fast Sector Erase Time – 300 ms

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase of a

Different Sector

– Supports Reading Any Byte/Word by Suspending Programming of Any Other

Byte/Word

Low-power Operation

– 30 mA Active

– 10 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Write Protection and Accelerated Program/Erase Operations

RESET Input for Device Initialization

Sector Lockdown Support

TSOP and CBGA Package Options

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

•

8-megabit

(512K x 16/

1M x 8)

3-volt Only

Flash Memory

AT49BV801

AT49BV801T

AT49LV801

AT49LV801T

Description

The AT49BV/LV801(T) is a 3.0-volt 8-megabit Flash memory organized as 524,288

words of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data appears on I/O0

- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 23 sectors for

erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA pack-

ages. The device has CE and OE control signals to avoid any bus contention. This

device can be read or reprogrammed using a single 2.65V power supply, making it

ideally suited for in-system programming.

Pin Configurations

Pin Name

A0 - A18

RESET

RDY/BUSY

VPP

I/O0 - I/O14

I/O15 (A-1)

BYTE

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

READY/BUSY Output

Write Protection and Power Supply for Accelerated Program/Erase

Operations

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

Rev. 3280A–FLASH–06/02

Device

Operation

READ:

The AT49BV/LV801(T) is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

When the device is first powered on, it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the “Command Definition in Hex” table on page 12 (I/O8 - I/O15 are

don’t care inputs for the command codes). The command sequences are written by applying a

low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address

is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the

first rising edge of CE or WE. Standard microprocessor write timings are used. The address

locations used in the command sequences are not affected by entering the command

sequences.

RESET:

A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high-impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE:

Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE:

The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into 23 sec-

tors (SA0 - SA22) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a sector is t

SEC

. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating in 2 µs.

BYTE/WORD PROGRAMMING:

Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

AT49BV/LV801(T)

3280A–FLASH–06/02

AT49BV/LV801(T)

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t

cycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the

erase or program operation was performed successfully.

VPP PIN:

The circuitry of the AT49BV/LV801(T) is designed so that the device can be pro-

grammed or erased from the V

power supply or from the VPP input pin. When V

is greater

than 1.65V and less than or equal to the VCC pin, the device selects the V

supply for pro-

gramming and erase operations. When the VPP pin is greater than the V

supply, the device

will select the V

input as the power supply for programming and erase operations. The

device will allow for some variations between the V

input and the V

power supply in its

selection of V

or V

for program or erase operations. If the VPP pin is within 0.3V of V

for

2.65V < V

< 3.6V, then the program or erase operations will use V

and disregard the V

input signal. When the V

signal is used for program and erase operations, the V

must be

in the 5V ± 0.5V or 12V ± 0.5V range to ensure proper operation. The V

pin cannot be left

floating.

PROGRAM/ERASE STATUS:

The device provides several bits to determine the status of a

program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11

and the following four sections describe the function of these bits. To provide greater flexibility

for system designers, the AT49BV/LV801(T) contains a programmable configuration register.

The configuration register allows the user to specify the status bit operation. The configuration

to “00”, the part will automatically return to the read mode after a successful program or erase

operation. If the configuration register is set to a “01”, a Product ID Exit command must be

given after a successful program or erase operation before the part will return to the read

mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,

any unsuccessful program or erase operation requires using the Product ID Exit command to

return the device to read mode. The default value (after power-up) for the configuration regis-

ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the

“Command Definition in Hex” table on page 12, the value of the configuration register can be

changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-

ter. The value of the configuration register will affect the operation of the I/O7 status bit as

described below.

DATA POLLING:

The AT49BV/LV801(T) features Data Polling to indicate the end of a pro-

gram cycle. If the status configuration register is set to a “00”, during a program cycle an

attempted read of the last byte/word loaded will result in the complement of the loaded data on

I/O7. Once the program cycle has been completed, true data is valid on all outputs and the

next cycle may begin. During a chip or sector erase operation, an attempt to read the device

will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read

from the device. Data Polling may begin at any time during the program cycle. Please see

“Status Bit Table” on page 11 for more details.

3280A–FLASH–06/02

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