SSTUA32864
1.8 V configurable registered buffer for DDR2-667 RDIMM
applications
Rev. 01 — 12 May 2005
Product data sheet
1. General description
The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed
for 1.7 V to 2.0 V V
DD
operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and un-driven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs
must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUA32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.
The SSTUA32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)
package.
Philips Semiconductors
SSTUA32864
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
Configurable register supporting DDR2 Registered DIMM applications
Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
Controlled output impedance drivers enable optimal signal integrity and speed
Exceeds SSTUA32864 JEDEC specification speed performance (1.8 ns max.
single-bit switching propagation delay; 2.0 ns max. mass-switching)
Supports up to 450 MHz clock frequency of operation
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
Supports SSTL_18 data inputs
Differential clock (CK and CK) inputs
Supports LVCMOS switching levels on the control and RESET inputs
Single 1.8 V supply operation (1.7 V to 2.0 V)
Available in 96-ball, 13.5
×
5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
s
400 MT/s to 667 MT/s DDR2 registered DIMMs without parity
4. Ordering information
Table 1:
Ordering information
T
amb
= 0
°
C to +70
°
C.
Type number
SSTUA32864EC/G
SSTUA32864EC
Solder process
Package
Name
Pb-free (SnAgCu
LFBGA96
solder ball compound)
SnPb solder ball
compound
LFBGA96
Description
plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5
×
5.5
×
1.05 mm
plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5
×
5.5
×
1.05 mm
Version
SOT536-1
SOT536-1
9397 750 14757
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 May 2005
2 of 19
Philips Semiconductors
SSTUA32864
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
5. Functional diagram
RESET
CK
CK
VREF
DCKE
SSTUA32864
1D
C1
R
QCKEA
QCKEB
(1)
DODT
1D
C1
R
QODTA
QODTB
(1)
DCS
1D
C1
R
QCSA
QCSB
(1)
CSR
D1
0
1
1D
C1
R
Q1A
Q1B
(1)
002aab383
to other channels
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUA32864; 1 : 2 mode (positive logic)
9397 750 14757
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 May 2005
3 of 19
Philips Semiconductors
SSTUA32864
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
6. Pinning information
6.1 Pinning
SSTUA32864EC/G
ball A1
SSTUA32864EC
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab384
Transparent top view
Fig 2. Pin configuration for LFBGA96
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DCKE
D2
D3
DODT
D5
D6
n.c.
CK
CK
D8
D9
D10
D11
D12
D13
D14
2
n.c.
D15
D16
n.c.
D17
D18
RESET
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
3
VREF
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
VREF
4
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
DD
5
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS
ZOH
Q8
Q9
Q10
Q11
Q12
Q13
Q14
6
DNU
Q15
Q16
DNU
Q17
Q18
C0
DNU
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
002aaa955
Fig 3. Ball mapping; 1 : 1 register (C0 = 0, C1 = 0); top view
9397 750 14757
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 May 2005
4 of 19
Philips Semiconductors
SSTUA32864
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DCKE
D2
D3
DODT
D5
D6
n.c.
CK
CK
D8
D9
D10
D11
D12
D13
D14
2
n.c.
DNU
DNU
n.c.
DNU
DNU
RESET
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
3
VREF
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
VREF
4
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
DD
5
QCKEA
Q2A
Q3A
QODTA
Q5A
Q6A
C1
QCSA
ZOH
Q8A
Q9A
Q10A
Q11A
Q12A
Q13A
Q14A
6
QCKEB
Q2B
Q3B
QODTB
Q5B
Q6B
C0
QCSB
ZOL
Q8B
Q9B
Q10B
Q11B
Q12B
Q13B
Q14B
002aaa956
Fig 4. Ball mapping; 1 : 2 register A (C0 = 0, C1 = 1); top view
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
D1
D2
D3
D4
D5
D6
n.c.
CK
CK
D8
D9
D10
DODT
D12
D13
DCKE
2
n.c.
DNU
DNU
n.c.
DNU
DNU
RESET
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
3
VREF
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
VREF
4
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
DD
5
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
QCSA
ZOH
Q8A
Q9A
Q10A
QODTA
Q12A
Q13A
QCKEA
6
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
QCSB
ZOL
Q8B
Q9B
Q10B
QODTB
Q12B
Q13B
QCKEB
002aaa957
Fig 5. Ball mapping; 1 : 2 register B (C0 = 1, C1 = 1); top view
9397 750 14757
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 May 2005
5 of 19
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