TC59SM716/08/04AS/ASL-70,-75,-80
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
2,097,152-WORDS
×
4 BANKS
×
16-BITS SYNCHRONOUS DYNAMIC RAM
4,194,304-WORDS
×
4 BANKS
×
8-BITS SYNCHRONOUS DYNAMIC RAM
8,388,608-WORDS
×
4 BANKS
×
4-BITS SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
TC59SM716AS/ASL is a CMOS synchronous dynamic random access memory organized as 2,097,152-words
×
4
banks
×
16 bits and TC59SM708AS/ASL is organized as 4,194,304 words
×
4 banks
×
8 bits and
TC59SM704AS/ASL is organized as 8,388,608 words
×
4 banks
×
4 bits. Fully synchronous operations are
referenced to the positive edges of clock input and can transfer data up to 143M words per second. These devices
are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as
a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable
Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices
are ideal for main memory in applications such as work-stations.
FEATURES
PARAMETER
-70
t
CK
Clock Cycle Time (min)
7 ns
40 ns
5.4 ns
56 ns
80 mA
100 mA
2 mA
TC59SM716/M708/M704
-75
7.5 ns
45 ns
5.4 ns
65 ns
75 mA
95 mA
2 mA
-80
8 ns
48 ns
6 ns
68 ns
70 mA
90 mA
2 mA
t
RAS
Active to Precharge Command Period (min)
t
AC
t
RC
Access Time from CLK (max)
Ref/Active to Ref/Active Command Period (min)
I
CC1
Operation Current (max) (Single bank)
I
CC4
Burst Operation Current (max)
I
CC6
Self-Refresh Current (max)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single power supply of 3.3 V
±
0.3 V
Up to 143 MHz clock frequency
Synchronous operations: All signals referenced to the positive edges of clock
Architecture:
Pipeline
Organization
TC59SM716AS/ASL:
2,097,152 words
×
4 banks
×
16 bits
TC59SM708AS/ASL:
4,194,304 words
×
4 banks
×
8 bits
TC59SM704AS/ASL:
8,388,608 words
×
4 banks
×
4 bits
Programmable Mode register
Auto Refresh and Self Refresh
Burst Length:
1, 2, 4, 8, Full page
CAS Latency:
2, 3
Single Write Mode
Burst Stop Function
Byte Data Controlled by L-DQM, U-DQM (TC59SM716)
4K Refresh cycles/64 ms
Interface:
LVTTL
Package
TC59SM716AS/ASL:
TSOPII54-P-400-0.4F
TC59SM708AS/ASL:
TSOPII54-P-400-0.4F
TC59SM704AS/ASL:
TSOPII54-P-400-0.4F
000707EBA2
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
2001-06-11
1/49
FPGA/CPLD
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