AL3P-67204V-55 datasheet, PDF - EEWORLD Datasheet

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AL3P-67204V-55: DescriptionFIFO, 4KX9, 55ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28; Categorystorage storage; File Size146KB，16 Pages; ManufacturerAtmel (Microchip)

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AL3P-67204V-55 Overview

FIFO, 4KX9, 55ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

AL3P-67204V-55 Parametric

Parameter Name	Attribute value
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	DIP,
Contacts	28
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	55 ns
period time	70 ns
JESD-30 code	R-PDIP-T28
length	37 mm
memory density	36864 bit
memory width	9
Number of functions	1
Number of terminals	28
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	4KX9
Exportable	NO
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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MATRA MHS

L 67203/L 67204

9 & 4K

9 / 3.3 Volts CMOS Parallel FIFO

Introduction

The L67203/204 implement a first-in first-out algorithm,

featuring asynchronous read/write operations. The FULL

and EMPTY flags prevent data overflow and underflow.

The Expansion logic allows unlimited expansion in word

size and depth with no timing penalties. Twin address

pointers automatically generate internal read and write

addresses, and no external address information are

required for the MHS FIFOs. Address pointers are

automatically incremented with the write pin and read

pin. The 9 bits wide data are used in data communications

applications where a parity bit for error checking is

necessary. The Retransmit pin resets the Read pointer to

zero without affecting the write pointer. This is very

useful for retransmitting data when an error is detected in

the system.

Using an array of eigh transistors (8 T) memory cell and

fabricated with the state of the art 1.0

µm

lithography

named SCMOS, the L 67203/204 combine an extremely

low standby supply current (typ = 1.0

µA)

with a fast

access time at 55 ns over the full temperature range. All

versions offer battery backup data retention capability

with a typical power consumption at less than 5

µW.

For military/space applications that demand superior

levels of performance and reliability the L 67203/204 is

processed according to the methods of the latest revision

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

Features

First-in first-out dual port memory

Single supply 3.3

0.3 volts

2048

9 organisation (L 67203)

4096

9 organisation (L 67204)

Fast access time

Commercial, industrial automotive and military :

55, 60, 65 ns

Wide temperature range : – 55

°C

to + 125

°C

67203L/204L low power

67203V/204V very low power

Fully expandable by word width or depth

Asynchronous read/write operations

Empty, full and half flags in single device mode

Retransmit capability

Bi-directional applications

Battery back-up operation 2 V data retention

TTL compatible

High performance SCMOS technology

Rev. C (10/11/94)

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