2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, DDRIIb4 SRAM
18Mb DDRII CIO SRAM
4-WORD BURST
Features
•
•
•
•
•
•
•
•
DLL circuitry for accurate output data placement
Pipelined, double data rate operation
Common data input/output bus
Fast clock to valid data times
Full data coherency, providing most current data
Four-tick burst for reduced-address frequency
Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
Simple control logic for easy depth expansion
Internally self-timed, registered writes
Core V
DD
= 1.8V (±0.1V); I/O V
DD
Q = 1.5V to V
DD
(±0.1V) HSTL
Clock-stop capability with µs restart
13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA
package
User-programmable impedance output
JTAG boundary scan
MT57W2MH8J
MT57W1MH18J
MT57W512H36J
Figure 1: 165-Ball FBGA
•
•
•
•
•
•
•
•
.
Table 1:
Valid Part Numbers
DESCRIPTION
2 Meg x 8, DDRIIb4 FBGA
1 Meg x 18, DDRIIb4 FBGA
512K x 36, DDRIIb4 FBGA
PART NUMBER
MT57W2MH8JF-xx
MT57W1MH18JF-xx
MT57W512H36JF-xx
Options
• Clock Cycle Timing
3ns (333 MHz)
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
2 Meg x 8
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0°C
£
T
A
£
+70°C)
NOTE:
Marking
1
-3
-3.3
-4
-5
-6
-7.5
MT57W2MH8J
MT57W1MH18J
MT57W512H36J
F
None
General Description
The Micron
®
DDRII synchronous, pipelined burst
SRAM employs high-speed, low-power CMOS designs
using an advanced 6T CMOS process.
The DDR SRAM integrates an SRAM core with
advanced synchronous peripheral circuitry and a burst
counter. All synchronous inputs pass through registers
controlled by an input clock pair (K and K#) and are
latched on the rising edge of K and K#. The synchro-
nous inputs include all addresses, all data inputs,
active LOW load (LD#), read/write (R/W#), and active
LOW byte writes or nibble writes (BWx# or NWx#).
Write data is registered on the rising edges of both K
and K#. Read data is driven on the rising edge of C and
C#, if provided, or on the rising edge of K and K# if C
and C# are not provided.
Asynchronous inputs include impedance match
(ZQ). Synchronous data outputs (Q, sharing the same
physical balls as the data inputs D) are tightly matched
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide
18Mb: 1.8V V
DD
, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
1
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, DDRIIb4 SRAM
to the output data clocks C and C#, eliminating the
need for separately capturing data from each individ-
ual DDR SRAM in the system design.
Additional write registers are incorporated to
enhance pipelined WRITE cycles and reduce READ-to-
WRITE turnaround time. WRITE cycles are self-timed.
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
The device can be used in HSTL systems by supply-
ing an appropriate reference voltage (V
REF
). The
device is ideally suited for applications requiring very
rapid data transfer by operation in data-doubled
mode. The device is also ideal in applications requiring
the cost benefits of pipelined CMOS SRAMs and the
reduced READ-to-WRITE turnaround times of Late
Write SRAMs.
The SRAM operates from a 1.8V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for cache, network, telecom,
DSP and other applications that benefit from a very
,
wide, high-speed data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
If a READ occurs after a WRITE cycle, address and
data for the write are stored in registers. The write
information must be stored because the SRAM cannot
perform the last word write to the array without con-
flicting with the read. The data stays in this register
until the next WRITE cycle occurs. On the first WRITE
cycle after the READ(s), the stored data from the earlier
WRITE will be written into the SRAM array. This is
called a posted write.
A read can be made immediately to an address even
if that address was written in the previous cycle. Dur-
ing this READ cycle, the SRAM array is bypassed, and
data is read instead from the data register storing the
recently written data. This is transparent to the user.
This feature facilitates system data coherency.
The DDR SRAM differs in some ways from its prede-
cessor, the Claymore DDR SRAM. Single data rate
operation is not supported, hence, no SD/DD# ball is
provided. Only bursts of four are supported. The need
for echo clocks is reduced or eliminated by the two sin-
gle-ended input clocks (C and C#), although tightly
controlled echo clocks (CQ and CQ#) are provided. The
SRAM synchronizes its output data to these data clock
rising edges, if provided. No differential clocks are used
in this device. This clocking scheme provides greater
system tuning capability than Claymore SRAMs and
reduces the number of input clocks required by the
bus master.
DDR Operation
The DDR SRAM enables high performance opera-
tion through high clock frequencies (achieved through
pipelining) and double data rate mode of operation. At
slower frequencies, the DDR SRAM requires a single
no-operation (NOP) cycle when transitioning from a
READ to a WRITE cycle. At higher frequencies, a sec-
ond NOP cycle may be required to prevent bus conten-
tion. NOP cycles are not required when switching from
a WRITE to a READ.
PARTIAL WRITE Operations
BYTE WRITE operations are supported, except for
x8 devices in which nibble write is supported. The
active LOW write controls, BWx# (NWx#), are regis-
tered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
18Mb: 1.8V V
DD
, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, DDRIIb4 SRAM
Programmable Impedance Output
Buffer
The DDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 350
W
resistor is required for an output
impedance of 70
W
. To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175
W
to 350
W
. Alternately, the ZQ ball
can be connected directly to V
DD
Q, which will place
the device in a minimum impedance mode.
Output impedance updates may be required
because, over time, variations may occur in supply
voltage and temperature. The device samples the value
of RQ. Impedance updates are transparent to the sys-
tem; they do not affect device operation, and all data
sheet timing and current specifications are met during
an update.
The device will power up with an output impedance
set at 50
W
. To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
Clock Considerations
This device utilizes internal delay-locked loops for
maximum output, data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry
automatically resets the DLL when the absence of
input clock is detected. See Micron Technical Note TN-
54-02 for more information on clock DLL start-up pro-
cedures.
Single Clock Mode
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
The output echo clocks are precise references to
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
Depth Expansion
Depth expansion requires replicating the LD# con-
trol signal for each bank. All other control signals can
be common between banks as appropriate.
18Mb: 1.8V V
DD
, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, DDRIIb4 SRAM
Figure 2: Functional Block Diagram
2 Meg x 8; 1 Meg x 18; 512K x 36
n
SA
LD#
n
E
ADDRESS
REGISTER
COMPARE
(NOTE 2)
n
n-2
SA1
SA1’
D1
Q1
SA0
SA0’
BURST
D0
Q0
LOGIC
CLK
(NOTE 1)
n
READ
WRITE#
n
WRITE#
SA0''
C
SA’
C#
OUTPUT
CONTROL
LOGIC
SA0'''
K
a
WRITE
E ADDRESS
REGISTER
INPUT
REGISTER
E
a
a
INPUT
REGISTER
E
n
SA0’
SA0#’
SA0’
a
CLK
WRITE
REGISTER
a
WRITE
DRIVER
a
a
SA0#’
SA0’
2n x a
MEMORY
ARRAY
a
SENSE
AMPS
a
a
C
a
OUTPUT
REGISTER
a
0
ZQ
a
a
OUTPUT
BUFFER
E
a
2
2:1
MUX
a
1
CQ, CQ#
DQ
a
a
a
K#
0
1
a
SA0''’
a
NWx#
BWx#
R/W#
R/W#
E REGISTER
WRITE#
OE
REGISTER
C
NOTE:
1. SA0 and SA1 are advanced in linear burst order at each K and K# rising edge.
2. The compare width is n – 2 bits. The compare is performed only if a WRITE is pending and a READ cycle is requested.
If the address matches, data is routed directly to the device outputs, bypassing the memory array.
3. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing
diagrams for detailed information.
4. For 2 Meg x 8, n = 21, a = 8; NWx# = 2 separate nibble writes.
For 1 Meg x 18, n = 20, a = 18; BWx# = 2 separate byte writes.
For 512K x 36, n = 19, a = 36; BWx# = 4 separate byte writes.
18Mb: 1.8V V
DD
, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG
X
8, 1 MEG
X
18, 512K
X
36
1.8V V
DD
, HSTL, DDRIIb4 SRAM
Figure 3: Application Example
R = 250Ω
R = 250Ω
SRAM 1
DQ
SA
ZQ
CQ
CQ#
DQ
SA
SRAM 2
ZQ
CQ
CQ#
LD# R/W# C C# K K#
LD# R/W# C C# K K#
DQ
Address
Cycle Start#
R/W#
Vt
R
Vt
BUS
SRAM 1 Input CQ#
MASTER
SRAM 2 Input CQ
(CPU
SRAM 2 Input CQ#
or
Source K
ASIC)
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
SRAM 1 Input CQ
NOTE:
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets setup
and hold times at the bus master.
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
18Mb: 1.8V V
DD
, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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