5962R-1020304VXC datasheet, PDF

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5962R-1020304VXC: Description2MX32 MULTI-PORT DEVICE SRAM MODULE, CQFP132, 0.900 X 0.900 INCH, SIDE BRAZED, CERAMIC, QFP-132; Categorystorage storage; File Size217KB，27 Pages; ManufacturerCobham Semiconductor Solutions

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5962R-1020304VXC Overview

2MX32 MULTI-PORT DEVICE SRAM MODULE, CQFP132, 0.900 X 0.900 INCH, SIDE BRAZED, CERAMIC, QFP-132

5962R-1020304VXC Parametric

Parameter Name	Attribute value
Maker	Cobham Semiconductor Solutions
Parts packaging code	QFP
package instruction	QFP,
Contacts	132
Reach Compliance Code	unknown
JESD-30 code	S-CQFP-G132
length	22.86 mm
memory density	67108864 bit
Memory IC Type	MULTI-PORT SRAM MODULE
memory width	32
Number of functions	1
Number of terminals	132
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-55 °C
organize	2MX32
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Filter level	MIL-STD-883 Class V
Maximum seat height	7.87 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.9 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
width	22.86 mm

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Standard Products

UT8ER1M32 32Megabit SRAM MCM

UT8ER2M32 64Megabit SRAM MCM

UT8ER4M32 128Megabit SRAM MCM

Preliminary Data Sheet

June 8, 2011

www.aeroflex.com/memories

FEATURES



20ns Read, 10ns Write maximum access times available



Functionally compatible with traditional 1M, 2M and 4M

x 32 SRAM devices



CMOS compatible input and output levels, three-state

bidirectional data bus

- I/O Voltages 2.3V to 3.6V, 1.7V to 2.0Vcore



Available densities:

- UT8ER1M32: 33, 554, 432 bits

- UT8ER2M32: 67, 108, 864 bits

- UT8ER4M32: 134, 217, 728 bits



Operational environment:

- Total-dose: 100 krad(Si)

- SEL Immune: 111MeV-cm

/mg

- SEU error rate = 6.0x10

-16

errors/bit-day assuming

geosynchronous orbit, Adam’s 90% worst environment,

and 6600ns default Scrub Rate Period (=97% SRAM

availability)



Packaging option:

- 132-lead side-brazed dual cavity ceramic quad flatpack



Standard Microelectronics Drawing:

- UT8ER1M32: 5962-10202

- QML Q, Q+ and Vcompliant

- UT8ER2M32: 5962-10203

- QML Q, Q+ and V pending

- UT8ER4M32: 5962-10204

- QML Q, Q+ and V pending

INTRODUCTION

The UT8ER1M32, UT8ER2M32, and UT8ER4M32 are high

performance CMOS static RAM multichip modules (MCMs)

organized as two, four or eight individual 524,288 words x 32

bits respectively. Easy memory expansion is provided by active

LOW chip enables (En), an active LOW output enable (G), and

three-state drivers. This device has a power-down feature that

reduces power consumption by more than 90% when deselected.

Autonomous (master) and demanded (slave) scrubbing

continues while deselected.

Writing to the device is accomplished by driving one of the chip

enable (En) inputs LOW and the write enable (W) input LOW.

Data on the 32 I/O pins (DQ0 through DQ31) is then written into

the location specified on the address pins (A0 through A18).

Reading from the device is accomplished by driving one of the

chip enables (En) and output enable (G) LOW while driving

write enable (W) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

Note:

Only on En pin may be active at any time.

The 32 input/output pins (DQ0 through DQ31) are placed in a

high impedance state when the device is deselected (En HIGH),

the outputs are disabled (G HIGH), or during a write operation

(En LOW, W LOW).

A[18:0]

512Kx32

(Master or Slave)

Die 1

DQ[31:0]

512Kx32

(Slave)

Die 2, 4, or 8

MBE

BUSY/NC

SCRUB

Figure 1. Block Diagram

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