U6264A
Standard 8K x 8 SRAM
Features
F
8192 x 8 bit static CMOS RAM
F
70 and 100 ns Access Times
F
Common data inputs and
F
F
F
ESD protection > 2000 V
F
F
F
F
F
F
F
F
F
F
outputs
Three-state outputs
Typ. operating supply current
70 ns: 45 mA
100 ns: 37 mA
Data retention current
at 3 V: < 10
µA
(standard)
Standby current standard < 30
µA
Standby current low power
(L) < 10
µA
Standby current very low power
(LL) < 1
µA
Standby current for LL-version
at 25
°C
and 5 V: typ. 50 nA
TTL/CMOS-compatible
Automatic reduction of power dis-
sipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
0 to 70
°C
-25 to 85
°C
-40 to 85
°C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
(MIL STD 883C M3015.7)
F
Latch-up immunity > 100 mA
F
Packages: PDIP28 (600 mil)
SOP28 (300 mil)
SOP28 (330 mil)
Description
The U6264A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The data outputs have
no preferred state. If the memory is
driven by CMOS levels in the
active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150
µA
typ.
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
PDIP
22
SOP
21
20
19
18
17
16
15
Top View
November 01, 2001
1
U6264A
Symbol
Switching Characteristics
Alt.
Time to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
LZ
t
WC
t
RC
t
ACE
t
OE
t
AA
t
WP
t
CW
t
AS
t
CW
t
WP
t
DS
t
DH
t
AH
t
OH
t
HZCE
t
HZWE
t
HZOE
IEC
t
t(QX)
t
cW
t
cR
t
a(E)
t
a(G)
t
a(A)
t
w(W)
t
w(E)
t
su(A)
t
su(E)
t
su(W)
t
su(D)
t
h(D)
t
h(A)
t
v(A)
t
dis(E)
t
dis(W)
t
dis(G)
07
5
10
5
07
10
10
10
ns
Min.
Max.
Unit
70
70
100
100
ns
ns
-
-
-
-
-
-
70
40
70
100
50
100
ns
ns
ns
50
65
70
90
ns
ns
0
65
50
35
0
0
5
0
0
0
0
90
70
40
0
0
5
0
0
0
25
30
25
35
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode E1-Controlled
V
CC
V
CC(DR)
≥
2 V
2.2 V
t
DR
0V
Data Retention
t
rec
2.2 V
E1
0V
Data Retention Mode E2-Controlled
V
CC
V
CC(DR)
≥
2 V
t
DR
0.8 V
Data Retention
V
E2(DR)
≤
0.2 V
t
rec
0.8 V
4.5 V
4.5 V
E2
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
t
DR
:
t
rec
:
min 0 ns
min t
cR
November 01, 2001
5
RF/Wirelessly
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