N25Q128A13TSF40F datasheet, PDF

Datasheet> All Categories > storage> storage> N25Q128A13TSF40F

N25Q128A13TSF40F: DescriptionFlash, 16MX8, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-16; Categorystorage storage; File Size6MB，183 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

Download Datasheet Parametric View All

N25Q128A13TSF40F Overview

Flash, 16MX8, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-16

N25Q128A13TSF40F Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	SOIC
package instruction	0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-16
Contacts	16
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
startup block	TOP
Maximum clock frequency (fCLK)	108 MHz
Data retention time - minimum	20
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G16
length	10.3 mm
memory density	134217728 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	16
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Serial bus type	SPI
Maximum standby current	0.0001 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
type	NOR TYPE
width	7.5 mm
write protect	HARDWARE/SOFTWARE

Preview

Download Datasheet

View All

N25Q128

128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors,

XiP enabled, serial flash memory with 108 MHz SPI bus interface

Features

SPI-compatible serial bus interface

108 MHz (maximum) clock frequency

2.7 V to 3.6 V single supply voltage

Supports legacy SPI protocol and new Quad

I/O or Dual I/O SPI protocol

Quad/Dual I/O instructions resulting in an

equivalent clock frequency up to 432 MHz:

XIP mode for all three protocols

– Configurable via volatile or non-volatile

registers:

Program/Erase suspend instructions

Continuous read (entire memory) via single

instruction:

– Fast Read

– Quad or Dual Output Fast Read

– Quad or Dual I/O Fast Read

Flexible to fit application:

– Configurable number of dummy cycles

– Output buffer configurable

– Fast POR instruction: decrease power-on

time

– Reset function (upon customer request)

64-byte user-lockable, one-time programmable

(OTP) area

Erase capability

– Subsector (4-Kbyte) granularity in the 8

boot sectors (bottom or top parts)

– Sector (64-Kbyte) granularity

Write protections

– Software write protection applicable to

every 64-Kbyte sector (volatile lock bit)

– Hardware write protection: protected area

size defined by non-volatile bits (BP0, BP1,

BP2, BP3 and TB bit)

– Additional smart protections available upon

customer request

Electronic signature

– JEDEC standard two-byte signature

(BA18h)

– Additional 2 Extended Device ID (EDID)

bytes to identify device factory options

– Unique ID code (UID) with 14 bytes read-

only, available upon customer request

More than 100,000 program/erase cycles per

sector

More than 20 years data retention

Packages (all packages RoHS compliant)

– F8 = VDFPN8 8 x 6 mm (MLP8)

– 12 = TBGA24 6 x 8 mm

– F6 = VDFPN8 6 x 5 mm (MLP)

– SF = SO16 (300 mils body width)

– SE = SO8W (SO8 208 mils body width)

May 2011

Micron Technology, Inc., reserves the right to change products or specifications without notice.

retfa yltcerid edom PiX selbane

Rev 7

no rewop

1/183

Contents

N25Q128 - 3 V

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write protect/enhanced program supply voltage (W/VPP), DQ2 . . . . . . . 18

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1

4.2

4.3

Extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

Extended SPI Protocol Operating features . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.1.8

5.1.9

5.1.10

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . 24

Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 24

Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 25

Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2

Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.1

Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

N25Q128 - 3 V

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

Contents

Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 28

Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 28

Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 28

HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3

Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

Multiple Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Quad Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

QUAD Command Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 30

Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 30

Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 31

HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

VPP pin Enhanced Supply Voltage feature . . . . . . . . . . . . . . . . . . . . . . 31

Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1

Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

BP3, BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2

Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12) . 37

XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 38

Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 38

Fast POR NV configuration bit (NVCR bit 5) . . . . . . . . . . . . . . . . . . . . . 38

Hold (Reset) disable NV configuration bit (NVCR bit 4) . . . . . . . . . . . . 38

Quad Input NV configuration bit (NVCR bit 3) . . . . . . . . . . . . . . . . . . . . 39

Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 39

6.3

Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3.1

6.3.2

Dummy clock cycle: VCR bits 7 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 42

6.4

Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 42

3/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Contents

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

N25Q128 - 3 V

Quad Input Command VECR<7> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Dual Input Command VECR<6> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Reset/Hold disable VECR<4> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3> . . . 44

Output Driver Strength VECR<2:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.5

Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

6.5.6

6.5.7

P/E Controller Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Erase Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Erase Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Program Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

VPP Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Program Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Protection Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.1

7.2

SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . . 49

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.1

Extended SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.1.7

9.1.8

9.1.9

9.1.10

9.1.11

9.1.12

9.1.13

9.1.14

9.1.15

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . 82

Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Dual I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Quad Output Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Quad I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Dual Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Quad Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Quad Input Extended Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

N25Q128 - 3 V

9.1.16

9.1.17

9.1.18

9.1.19

9.1.20

9.1.21

9.1.22

9.1.23

9.1.24

9.1.25

9.1.26

9.1.27

9.1.28

9.1.29

9.1.30

9.1.31

9.1.32

9.1.33

Contents

Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Read NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Write NV Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 111

Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 111

9.2

DIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.2.8

9.2.9

9.2.10

9.2.11

9.2.12

9.2.13

9.2.14

9.2.15

9.2.16

9.2.17

9.2.18

Multiple I/O Read Identification protocol . . . . . . . . . . . . . . . . . . . . . . . 114

Dual Command Fast Read (DCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Dual Command Page Program (DCPP) . . . . . . . . . . . . . . . . . . . . . . . 117

Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Program/Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Program/Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Recommended Resources

Make a dream lamp with CD4069

Two practical password controller circuits b

TA7283AP power amplifier circuit diagram

555 simple switching regulator circuit

Threshold signal generator circuit using TcA965

Telephone remote ringing circuit

How smart stores equipped with multiple sensors make shopping a breeze: It's a Friday evening and you decide to make fish tacos, so you pop into your local supermarket on your way home from get off work. It only takes a few minutes to find the cilantro, or, more accuratel...; alan000345 TI Technology Forum

M57957L/M57958LIGBT Thick Film Driver IC: Both M57957L and M57958L adopt single in-line standard 8-pin thick film integrated circuit package...; zbz0529 Analog electronics

Serial port transparent transmission Bluetooth: ...; gaoyang9992006 RF/Wirelessly

Does anyone have a program to display a waveform or bar graph on the TFT screen of the TI LM3S series?: Help:Does anyone have a program to display a waveform or bar graph on the TFT screen of the TI LM3S series? I heard that some TI series have waveform display programs, but the 9B92 I use does not have...; zhangyao Microcontroller MCU

[If you could choose again] If you could choose again, would you choose to continue working as an EE, or choose a state-owned enterprise that can provide you with retirement benefits?: 1. I want to go to a retirement home, and I want to go to various retirement units, such as state-owned enterprises, civil servants, and public institutions near my home. 2. I still insist on my choic...; wb930129 Talking

"Corelinks" free development board giveaway event suspended and the fourth prize results announced! !: [i=s]This post was last edited by Corelinks on 2014-9-29 12:52[/i] [size=4] Due to the holiday, the four-phase free development board giveaway event has been suspended. I hope everyone can relax and h...; 芯灵思 Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components