Freescale Semiconductor
Technical Data
MPC7447AEC
Rev. 5, 01/2006
MPC7447A
RISC Microprocessor
Hardware Specifications
This document is primarily concerned with the PowerPC™
MPC7447A; however, unless otherwise noted, all
information here also applies to the MPC7447. The
MPC7447A is an implementation of the PowerPC
microprocessor family of reduced instruction set computer
(RISC) microprocessors. This document describes pertinent
electrical and physical characteristics of the MPC7447A. For
functional characteristics of the processor, refer to the
MPC7450 RISC Microprocessor Family Reference Manual.
To locate any published updates for this document, refer to
the Freescale website located at
http://www.freescale.com.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Comparison with the MPC7447, MPC7445, and
MPC7441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical and Thermal Characteristics . . . . . . . . . . . . 9
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 27
System Design Information . . . . . . . . . . . . . . . . . . . 34
Document Revision History . . . . . . . . . . . . . . . . . . . 52
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 52
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
1
Overview
The MPC7447A is the fifth implementation of the
fourth-generation (G4) microprocessors from Freescale. The
MPC7447A implements the full PowerPC 32-bit
architecture and is targeted at networking and computing
systems applications. The MPC7447A consists of a
processor core and a 512-Kbyte L2.
Figure 1
shows a block diagram of the MPC7447A. The core
is a high-performance superscalar design supporting a
double-precision floating-point unit and a SIMD multimedia
unit. The memory storage subsystem supports the MPX bus
protocol and a subset of the 60x bus protocol to main
memory and other system resources.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
2
Instruction Unit
Branch Processing Unit
Fetcher
Tags
IBAT Array
BHT (2048-Entry)
Dispatch
Unit
Data MMU
SRs
(Original)
VR Issue
(4-Entry/2-Issue)
DBAT Array
GPR Issue
(6-Entry/3-Issue)
FPR Issue
(2-Entry/1-Issue)
128-Entry
DTLB
Tags
LR
BTIC (128-Entry)
CTR
Instruction Queue
(12-Word)
SRs
(Shadow)
128-Entry
ITLB
Instruction MMU
128-Bit (4 Instructions)
32-Kbyte
I Cache
32-Kbyte
D Cache
Reservation
Stations (2-Entry)
EA
Load/Store Unit
Vector Touch Engine
+ (EA Calculation)
Finished
Stores
L1 Castout
PA
FPR File
16 Rename
Buffers
Reservation
Stations (2)
Completes up
to three
instructions
per clock
VR File
16 Rename
Buffers
Integer
Unit 2
x÷
Vector
FPU
32-Bit
128-Bit
128-Bit
+++
32-Bit
32-Bit
Integer
Integer
Integer
Unit 122
Unit
Unit
(3)
16 Rename
Buffers
Reservation
Stations (2)
GPR File
Reservation
Reservation
Reservation
Station
Station
Station
Vector
Touch
Queue
Floating-
Point Unit
L1 Push
Completed
Stores
+ x÷
FPSCR
Load Miss
64-Bit
64-Bit
Vector
Integer
Unit 1
512-Kbyte Unified L2 Cache Controller
System Bus Interface
Load
Queue (11)
Overview
Additional Features
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
• Dynamic Frequency Switching (DFS)
• Temperature Diode
Completion Unit
96-Bit (3 Instructions)
Completion Queue
(16-Entry)
Reservation Reservation Reservation Reservation
Station
Station
Station
Station
Figure 1. MPC7447A Block Diagram
L1 Service
Queues
Line
Block 0 (32-Byte)
Block 1 (32-Byte)
Tags Status
Status
L1 Castouts
(4)
L2 Store Queue (L2SQ)
Snoop Push/
Interventions
Vector
Permute
Unit
Vector
Integer
Unit 2
Memory Subsystem
L1 Store Queue
(LSQ)
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
L1 Load Queue (LLQ)
L1 Load Miss (5)
Bus Store Queue
Castout
Queue (5) /
Push
Queue (6)
1
Bus Accumulator
L2 Prefetch (3)
Instruction Fetch (2)
Cacheable Store Miss (1)
36-Bit
Address Bus
64-Bit
Data Bus
Freescale Semiconductor
Notes:
The Castout Queue and Push Queue share resources such that they have a combined total of 6 entries.
The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
Features
NOTE
The MPC7447A is a footprint-compatible, drop-in replacement in an
MPC7447 application if the core power supply is 1.3 V.
2
Features
This section summarizes features of the MPC7447A implementation of the PowerPC architecture.
Major features of the MPC7447A are as follows:
•
High-performance, superscalar microprocessor
— Up to four instructions can be fetched from the instruction cache at a time.
— Up to 12 instructions can be in the instruction queue (IQ).
— Up to 16 instructions can be at some stage of execution simultaneously.
— Single-cycle execution for most instructions
— One instruction per clock cycle throughput for most instructions
— Seven-stage pipeline control
Eleven independent execution units and three register files
— Branch processing unit (BPU) features static and dynamic branch prediction
– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache
of branch instructions that have been encountered in branch/loop code sequences. If a target
instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can
be made available from the instruction cache. Typically, a fetch that hits the BTIC provides
the first four instructions in the target stream.
– 2048-entry branch history table (BHT) with 2 bits per entry for four levels of
prediction—not taken, strongly not taken, taken, and strongly taken
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are
often removed from the instruction stream.
– Eight-entry link register stack to predict the target address of Branch Conditional to Link
Register (bclr) instructions
— Four integer units (IUs) that share 32 GPRs for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions.
– IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions.
— Five-stage FPU and a 32-entry FPR file
– Fully IEEE 754-1985–compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
3
•
Features
•
•
•
•
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as
vector add instructions (for example,
vaddsbs, vaddshs,
and
vaddsws).
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example,
vmhaddshs, vmhraddshs,
and
vmladduhm).
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
– 3-cycle GPR and AltiVec load latency (byte, half word, word, vector) with 1-cycle
throughput
– 4-cycle FPR load latency (single, double) with 1-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2.
— A maximum of three instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to dispatch. (This includes instructions that
are assigned a space in the CQ but not in an issue queue.)
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
Dispatch unit
— Decode/dispatch stage fully decodes each instruction
Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
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Freescale Semiconductor
Features
•
•
•
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for
icbi
instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total 9-cycle load latency for an L1 data cache miss that hits in L2
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address, 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set-associative, and use an LRU replacement algorithm.
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
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