AT17LV65-10CL datasheet, PDF - EEWORLD Datasheet

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AT17LV65-10CL: DescriptionConfiguration Memory, 64KX1, Serial, CMOS, 6 X 6 MM, 1.04 MM HEIGHT, 1.27 MM PITCH, LAP-8; Categorystorage storage; File Size412KB，29 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT17LV65-10CL Overview

Configuration Memory, 64KX1, Serial, CMOS, 6 X 6 MM, 1.04 MM HEIGHT, 1.27 MM PITCH, LAP-8

AT17LV65-10CL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	SOIC
package instruction	SON,
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	IT CAN OPERATES ON 4.75-5.25 RANGE SUPPLY VOLTAGE ALSO
Maximum clock frequency (fCLK)	10 MHz
JESD-30 code	S-XDSO-N8
length	5.99 mm
memory density	65536 bit
Memory IC Type	CONFIGURATION MEMORY
memory width	1
Number of functions	1
Number of terminals	8
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX1
Package body material	UNSPECIFIED
encapsulated code	SON
Package shape	SQUARE
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.14 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	COPPER NICKEL GOLD
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	5.99 mm

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Features

•

EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,

2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration

Programs for Field Programmable Gate Arrays (FPGAs)

Supports both 3.3V and 5.0V Operating Voltage Applications

In-System Programmable (ISP) via Two-Wire Bus

Simple Interface to SRAM FPGAs

Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera

FLEX

, APEX

™

Devices, ORCA

, Xilinx

XC3000, XC4000, XC5200, Spartan

, Virtex

™

FPGAs

Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

Very Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and

44-lead TQFP Packages

Emulation of Atmel’s AT24CXXX Serial EEPROMs

Low-power Standby Mode

High-reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for

Commercial Parts (at 70°C)

Green (Pb/Halide-free/RoHS Compliant) Package Options Available

•

FPGA

Configuration

EEPROM

Memory

AT17LV65

AT17LV128

AT17LV256

AT17LV512

AT17LV010

AT17LV002

AT17LV040

3.3V and 5V

System Support

•

1. Description

The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-

to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The

AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-

lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see

Table 1-1.

The

AT17LV series Configurators uses a simple serial-access procedure to configure one

or more FPGA devices. The user can select the polarity of the reset function by pro-

gramming four EEPROM bytes. These devices also support a write-protection

mechanism within its programming mode.

The AT17LV series configurators can be programmed with industry-standard pro-

grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

2321H–CNFG–03/06

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