K4S643233E-SE/N
CMOS SDRAM
2M x 32 SDRAM
512K x 32bit x 4 Banks
Synchronous DRAM
LVTTL(3.0V & 3.3V)
Extended Temperature
90-Ball FBGA
Revision 1.5
April 2002
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.5 April 2002
K4S643233E-SE/N
Revision History
Revision 1.5 (April 19, 2002) -
Final
• Erased TSOP specification.
CMOS SDRAM
Revision 1.4 (November 15, 2001) -
Final
• Final specification for 2Mx32 SDRAM.
Revision 1.3 (October 10, 2001) -
Preliminary
• Integrated 3.0V part numbr(K4S643234E-S(T)E(N)) and 3.3V part number(K4S643232E-S(T)E(N)) to 3.0V & 3.3V part-
number(K4S643233E-S(T)E(N)).
• Deleted tCC 5ns part and 6ns part.
• Unification of tCH 3ns for -70 part and tCH 3ns for -80 part, tCH 3ns for -10 part.
• Unification of tCL 3ns for -70 part and tCL 3ns for -80 part, tCL 3ns for -10 part.
• Unification of tSS 1.75ns for -70 part and tSS 2ns for -80 part, tSS 2.5ns for -10 part.
• Changed tCDL form 2clk to 1clk and tRDL for CL1 from 1clk to 2clk.
Revision 1.2 (August 7, 2001) -
Target
• Added CAS Latency 1
Revision 1.1 (July 6, 2001)
• Added K4S643232E-T/S(E/N)50
Revision 1.0 (April 6, 2001)
Revision 0.0 (March 21, 2001)
•
•
•
•
Initial draft
Extended temperature (-25
°
c ~ 85
°
c )
3.3V Power supply (VDD &VDDQ)
Supported 90-ball FBGA as well as 86 - TSOP
-2-
Rev. 1.5 April 2002
K4S643233E-SE/N
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
•
•
•
•
3.0V & 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1 & 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle).
CMOS SDRAM
GENERAL DESCRIPTION
The K4S643233E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
•
•
•
•
•
ORDERING INFORMATION
Part NO.
K4S643233E-SE/N70
K4S643233E-SE/N80
K4S643233E-SE/N10
Max Freq.
143MHz
125MHz
100MHz
Interface
LVTTL
Package
90-Ball
FBGA
• Extended Temperature range : -25
o
C to +85
o
C.
- SE/N : Extended temperature (-25
o
C - 85
o
C )
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
512K x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
-3-
Rev. 1.5 April 2002
K4S643233E-SE/N
90-Ball FBGA Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
9
A
e
B
C
D
D
E
F
G
D
1
H
J
K
D/2
L
M
N
P
R
E
E/2
8
7
6
5
4
3
2
1
CMOS SDRAM
< Top View
*2
>
90Ball(6x15) CSP
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
DQ28
V
SSQ
V
SSQ
V
DDQ
V
SS
A4
A7
CLK
DQM1
V
DDQ
V
SSQ
V
SSQ
DQ11
DQ13
2
DQ24
V
DDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
V
DDQ
DQ15
3
V
SS
V
SSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
V
SS
DQ9
DQ14
V
SSQ
V
SS
7
V
D D
V
DDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS
V
D D
DQ6
DQ1
V
DDQ
V
D D
8
DQ23
V
SSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
V
SSQ
DQ0
9
DQ21
DQ19
V
DDQ
V
DDQ
V
SSQ
V
D D
A1
NC
RAS
DQM0
V
SSQ
V
DDQ
V
DDQ
DQ4
DQ2
*2: Top View
Pin Name
CLK
CS
CKE
A
A1
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
A
0
~ A
10
BA
0
~ BA
1
RAS
CAS
WE
DQM
0
~ DQM
3
DQ
0
~
31
V
DD
/V
SS
V
DDQ
/V
SSQ
Substrate(2 Layer)
ϕ
b
ζ
*1: Bottom View
< Top
View
*2
>
#A1 Ball Origin Indicator
SEC
Week
K4S643233E
Symbol
A
A
1
E
E
1
D
D
1
e
ϕb
ζ
Min
-
0.30
-
-
-
-
-
0.40
-
Typ
1.40
0.35
11.00
6.40
13.00
11.20
0.80
0.45
-
Max
1.45
0.40
-
-
-
-
-
0.50
0.10
SXXX
-4-
Rev. 1.5 April 2002
K4S643233E-SE/N
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
D D
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
O U T
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
•Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25
o
C to +85
o
C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
2.7
2.0
-0.3
2.4
-
-10
Typ
3.0
3.0
0
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(V
D D
= 3.0 & 3.3V, T
A
= 23°C, f = 1MHz, V
REF
= 1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
I N
C
ADD
C
OUT
Min
-
-
-
-
Max
4
4.5
4.5
6.5
Unit
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
0
~ DQ
31
-5-
Rev. 1.5 April 2002