.
IBM0418A8CFLBB
IBM0418A4CFLBB
Preliminary
IBM0436A8CFLBB
IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• CMOS Technology
• Double Data Rate and Single Data Rate Syn-
chronous Modes of Operation
• Pipeline Mode of Operation
• Self-Timed Late Write with Full Data Coherency
• Single Differential Extended HSTL Clock
• +2.5V Power Supply, Ground, 1.6V V
DDQ
, and
1.05V V
REF
• Extended HSTL Input
• HSTL Outputs
• Registered Addresses, Controls, and Data Ins
• Burst Mode of operation
• Common I/O
• Asynchronous Output Enable
• Boundary Scan using limited set of JTAG
1149.1 functions
• 9 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• Programmable Impedance Output Drivers
Description
The IBM0436A4CFLBB, IBM0418A4CFLBB,
IBM0418A8CFLBB, and IBM0436A8CFLBB
SRAM
S
are Synchronous Pipeline Mode, high-per-
formance CMOS Static Random Access Memories
that are versatile, have wide I/O, and achieve 3.0ns
cycle times. Differential CK clocks are used to ini-
tiate the read/write operation and all internal opera-
tions are self-timed. At the rising edge of the CK
clock, all Addresses, Controls, and Data Ins are reg-
istered internally. Data Outs are updated from out-
put registers off the next rising and falling edge of
the K clock, hence the Double Data Rate. Internal
Write buffers allow write data to follow one cycle
after addresses and controls. The chip is operated
with a single +2.5V power supply and is compatible
with HSTL I/O interfaces.
cddrh251620.07
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 26
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
x36 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
2
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
3
SA
SA
SA
NC
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
NC
V
DD
SA
TMS
4
SA
V
SS
SA
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
LBO
V
DD
V
DD
V
SS
SA
V
SS
TDI
5
ZQ
B1(LD)
G
V
DD
V
REF
V
DD
CK
CK
V
DD
B2(WE)
B3(DDR)
V
DD
V
REF
V
DD
SA1
SA0
TCK
6
SA
V
SS
SA
VSS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
NC
V
DD
V
DD
V
SS
SA
V
SS
TDO
7
SA
SA
SA
SA(8M)
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
SA
V
DD
SA
NC
8
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
9
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
x18 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
2
V
DDQ
DQ
V
DDQ
NC
V
DDQ
CQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
3
SA
SA
SA
NC
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
SA
V
DD
SA
TMS
4
SA
V
SS
SA
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
LBO
V
DD
V
DD
V
SS
SA
V
SS
TDI
5
ZQ
B1(LD)
G
V
DD
V
REF
V
DD
CK
CK
V
DD
B2(WE)
B3(DDR)
V
DD
V
REF
V
DD
SA1
SA0
TCK
6
SA
V
SS
SA
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
NC
V
DD
V
DD
V
SS
SA
V
SS
TDO
7
SA
SA
SA
SA(8M)
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
SA
V
DD
SA
NC
8
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
CQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
9
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
cddrh251620.07
12/00
Page 2 of 26
Preliminary
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Inputs
SA0-SA1 Burst control starting addresses
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
Output Differential Echo Clocks
Differential Input Register Clocks
Synchronous Function Control Input. B1 = 0
Loads a new Address
Synchronous Function Control Input (WE). B2
= 0 starts Write & B2 = 1 starts Read.
Synchronous Function Control Input. B3 = 0
starts a DDR (Burst) operation. B3 = 1 starts a
SDR (Single Data Rate)
Linear Burst Order, (LBO =1 interleave mode,
LBO = 0 linear mode)
Asynchronous Output Enable
SA0-SA18
TMS,TDI,TCK IEEE 1149.1 Test Inputs (LVTTL levels)
DQ0-DQ35
TDO
IEEE 1149.1 Test Output (LVTTL level)
CQ, CQ
CK, CK
B1
V
REF
(2)
V
DD
V
SS
V
DDQ
Extended HSTL Input Reference Voltage
Power Supply (+2.5V)
Ground
B2
Output Power Supply
B3
ZQ
Input pin for Output Driver Impedance Control.
LBO
G
NC
No Connect
cddrh251620.07
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 26
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Ordering Information
Part Number
IBM0418A4CFLBB-3P
IBM0418A4CFLBB-3
IBM0418A4CFLBB-4
IBM0418A4CFLBB-4H
IBM0418A4CFLBB-5
IBM0436A4CFLBB-3P
IBM0436A4CFLBB-3
IBM0436A4CFLBB-4
IBM0436A4CFLBB-4H
IBM0436A4CFLBB-5
IBM0418A8CFLBB-3P
IBM0418A8CFLBB-3
IBM0418A8CFLBB-4
IBM0418A8CFLBB-4H
IBM0418A8CFLBB-5
IBM0436A8CFLBB-3P
IBM0436A8CFLBB-3
IBM0436A8CFLBB-4
IBM0436A8CFLBB-4H
IBM0436A8CFLBB-5
Organization
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
Speed
1.7ns Access / 3.0ns Cycle
1.8ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.0ns Access / 4.5ns Cycle
2.5ns Access / 5.0ns Cycle
1.7ns Access / 3.0ns Cycle
1.8ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.0ns Access / 4.5ns Cycle
2.5ns Access / 4.5ns Cycle
1.7ns Access / 3.0ns Cycle
1.8ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.0ns Access / 4.5ns Cycle
2.5ns Access / 4.5ns Cycle
1.7ns Access / 3.0ns Cycle
1.8ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.0ns Access / 4.5ns Cycle
2.5ns Access / 4.5ns Cycle
Leads
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
9 x 17 BGA
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
cddrh251620.07
12/00
Page 4 of 26
Preliminary
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Block Diagram
(x36 Double Data Rate Mode)
SA0-SA18
Read
Address
E Register
A2-A18
Write
Address
E Register
2:1 MUX
Decode
128Kx72
Array
36
36
36
36
A0,A1
CK, CK
Load
Advance
E
A0’, A1’
Burst
Logic
A0’
Compare
Match
0
V
SS
Output
REG
36
Output
REG
1
0
36
Output
REG
1
0
1
0
1
A0’
A0’
V
DD
Output
REG
B1-B3
Control
Logic
Write
1
0
1
0
Write
Buffer
E
0
1
A0’
0
1
Write
Buffer
E
4
G
Output Enable
4
36
36
36
36
CQa, CQa
CQb, CQb
DQ0-DQ35
cddrh251620.07
12/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 26