Crystal-to-LVDS Clock Synthesizer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2016
ICS844625I
DATA SHEET
General Description
The ICS844625I is a high frequency clock generator. The
ICS844625I uses an external 25MHz crystal to synthesize
312.5MHz, 156.25MHz and 125MHz clocks. The ICS844625I has
excellent cycle-to-cycle and RMS period jitter performance.
The ICS844625I operates at full 3.3V, 2.5V or mixed 3.3V, 2.5V
supply modes and is available in a fully RoHS compliant 48-lead
TQFP, E-Pad package.
Features
•
•
•
•
•
•
•
•
Ten selectable differential LVDS outputs
Output frequencies of 312.5MHz, 156.25MHz or 125MHz using a
25MHz crystal.
Crystal oscillator interface designed for 18pF, 25MHz parallel
resonant crystal
Cycle-to-cycle jitter: 13ps (typical)
RMS phase jitter at 125MHz (1.875MHz - 20MHz):
0.417ps (typical), V
DD
= 3.3V
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.387ps (typical), V
DD
= 3.3V
Output duty cycle: 50%, (typical)
Supply modes:
V
DD
/ V
DDA
/ V
DDO
3.3V / 3.3V / 3.3V
2.5V / 2.5V / 2.5V
3.3V / 3.3V / 2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement use 849S625i
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•
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Frequency Table for Bank A, B and C Outputs
Crystal Frequency (MHz)
25
25
25
Feedback Divider
25
25
25
VCO Frequency (MHz)
625
625
625
Output Divider
÷2
÷4
÷5
Output Frequency (MHz)
312.5
156.25
125
Pin Assignment
V
DD
REF_CLK
GND
BYPASS
MR
nc
SELA0
SELA1
V
DDA
QA0
nQA0
V
DDO
XTAL_IN
XTAL_OUT
GND
SELC0
SELC1
OEA
V
DD
OEB
OEC
SELB0
SELB1
GND
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
5
48 Lead TQFP, E-Pad
32
6
31
7mm x 7mm x 1.0mm
30
7
package body
8
29
9
28
Y Package
10
27
Top View
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
ICS844625I
QA1
nQA1
QA2
nQA2
V
DDO
GND
QA3
nQA3
QA4
nQA4
QA5
nQA5
QC1
nQC0
QC0
nc
V
DDO
nQB1
QB1
nQB0
QB0
V
DDO
nQC1
ICS844625BYI REVISION A JUNE 3, 2016
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©2016 Integrated Device Technology, Inc.
V
DDO
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Block Diagram
OEA
SELA[0:1]
BYPASS
REF_CLK
25MHz
Pullup
Pulldown
Pulldown
2
Pulldown
1
6
÷2, ÷4, ÷5
QA[0:5]
nQA[0:5]
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
625MHz
0
M = ÷25
MR
OEB
SELB[0:1]
Pulldown
Pullup
Pulldown
2
÷2, ÷4, ÷5
2
QB[0:1]
nQB[0:1]
2
÷2, ÷4, ÷5
SELC[0:1]
OEC
Pulldown
Pullup
QC[0:1]
nQC[0:1]
2
ICS844625BYI REVISION A JUNE 3, 2016
2
©2016 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1,
2
3, 12, 31, 46
4,
5
6
7, 48
8
Name
XTAL_IN
XTAL_OUT
GND
SELC0,
SELC1
OEA
V
DD
OEB
Input
Power
Input
Pulldown
Type
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Power supply pins.
Selects the output divider value. See Table 3C.
LVCMOS/LVTTL interface levels.
Active high output enable. When logic HIGH, Bank A outputs are enabled
and active. When logic LOW, the outputs are disabled and forced to
HIGH/LOW. LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup
Active high output enable. When logic HIGH, Bank B outputs are enabled
and active. When logic LOW, the outputs are disabled and forced to
HIGH/LOW. LVCMOS/LVTTL interface levels.
Active high output enable. When logic HIGH, Bank C outputs are enabled
and active. When logic LOW, the outputs are disabled and forced to
HIGH/LOW. LVCMOS/LVTTL interface levels.
Selects the output divider value. See Table 3B.
LVCMOS/LVTTL interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
No connect.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Analog supply pin.
Pulldown
Pulldown
Pulldown
Pulldown
Selects the output divider value. See Table 3A.
LVCMOS/LVTTL interface levels.
Master Reset. LVCMOS/LVTTL interface levels.
BYPASS signal allows to bypass the PLL. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Input
Power
Input
Pullup
9
10,
11
13, 19, 24,
32, 37
14, 15
16, 17
18, 43
20, 21
22, 23
25, 26
27, 28
29, 30
33, 34
35, 36
38, 39
40
41,
42
44
45
47
OEC
SELB0,
SELB1
V
DDO
nQC1, QC1
nQC0, QC0
nc
nQB1, QB1
nQB0, QB0
nQA5, QA5
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
V
DDA
SELA1,
SELA0
MR
BYPASS
REF_CLK
Input
Pullup
Input
Power
Output
Output
Unused
Output
Output
Output
Output
Output
Output
Output
Output
Power
Input
Input
Input
Input
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
ICS844625BYI REVISION A JUNE 3, 2016
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©2016 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. SELA Function Table
Input
SELA0
0
0
1
1
SELA1
0
1
0
1
Bank A Output Divider
N/A
÷2
÷4
÷5
Table 3B. SELB Function Table
Input
SELB0
0
0
1
1
SELB1
0
1
0
1
Bank B Output Divider
N/A
÷2
÷4
÷5
Table 3C. SELC Function Table
Input
SELC0
0
0
1
1
SELC1
0
1
0
1
Bank C Output Divider
N/A
÷2
÷4
÷5
ICS844625BYI REVISION A JUNE 3, 2016
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©2016 Integrated Device Technology, Inc.
ICS844625I Data Sheet
CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, LVDS I
O
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
10mA
15mA
29C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
=
-40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.31
3.135
Typical
3.3
2.5
3.3
101
25
113
Maximum
3.465
V
DD
3.465
125
31
140
Units
V
V
V
mA
mA
mA
Table 4B. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
=
-40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.21
2.375
Typical
2.5
2.5
2.5
96
17
95
Maximum
2.625
V
DD
2.625
120
21
128
Units
V
V
V
mA
mA
mA
ICS844625BYI REVISION A JUNE 3, 2016
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©2016 Integrated Device Technology, Inc.