845264AKILFT datasheet, PDF - EEWORLD Datasheet

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845264AKILFT: DescriptionVFQFPN-32, Reel; CategoryThe embedded processor and controller Microcontrollers and processors; File Size573KB，24 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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845264AKILFT Overview

VFQFPN-32, Reel

845264AKILFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	VFQFN-32
Contacts	32
Manufacturer packaging code	NLG32P1
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	ALSO OPERTES AT 3.3V SUPPLY
JESD-30 code	S-XQCC-N32
JESD-609 code	e3
length	5 mm
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	312.5 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	25 MHz
Maximum seat height	1 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

845264AKILFT Preview

FemtoClock

Crystal-to-CML Clock Generator

845264

DATA SHEET

General Description

The 845264 is a 3.3V, 2.5V CML clock generator designed for

Ethernet applications. The device synthesizes four clock frequencies

on two separately selectable output banks. Each bank has either a

62.5MHz, 125MHz, 156.25MHz or 312.5MHz clock signal with

excellent phase jitter performance. Each clock frequency is

distributed to two low-skew differential CML output banks with a total

of four outputs. The device is suitable for driving the reference clocks

of Ethernet PHYs. The device supports 3.3V and 2.5V voltage

supply and is packaged in a small, lead-free (RoHS 6) 32-lead

VFQFN package. The extended temperature range supports

telecommunication, wireless infrastructure and networking end

equipment requirements.

Features

•

Clock generation of: 62.5MHz, 125MHz, 156.25MHz and

312.5MHz

Two banks of two differential CML clock outputs

Crystal interface designed for 25MHz, 12pF parallel resonant

crystal

RMS phase jitter @ 125MHz, using a 25MHz crystal

(1.875MHz – 20MHz): 0.486ps (typical)

Offset

Single-side Band Phase Noise

100Hz ............................-97 dBc/Hz

1kHz...............................-118 dBc/Hz

10kHz.............................-125 dBc/Hz

100kHz...........................-123 dBc/Hz

•

LVCMOS interface levels for the control inputs

Full 3.3V and 2.5V supply voltage

Lead-free (RoHS 6) 32 VFQFN packaging

-40°C to 85°C ambient operating temperature

Block Diagram

nOEA

FSELA[1:0]

XTAL_IN

OSC

XTAL_OUT

REF_CLK

REF_SEL

nBYPASS

FSELB[1:0]

nOEB

Pulldown

Pullup

Pulldown

Pin Assignment

nQA1

nQB1

GND

QA1

QB1

nOEB

32 31 30 29 28 27 26 25

Phase

REF

Detector

VCO

÷2, ÷4,

÷5, ÷10

QA0

nQA0

QA1

nQA1

QB0

nQB0

QB1

nQB1

nQA0

QA0

nOEA

nQB0

QB0

REF_SEL

FSELA1

FSELA0

FSELB1

FSELB0

845264

÷25

÷2, ÷4,

÷5, ÷10

10 11 12 13 14 15 16

XTAL_OUT

nBYPASS

REF_CLK

XTAL_IN

DDA

GND

32 lead, 5mm x 5mm VFQFN

845264 REVISION B 07/20/15

845264 DATA SHEET

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

Number

1, 2

3, 17

5, 6, 7, 8, 9,

16, 25, 32

13, 29

14,

18,

20,

23, 24

27, 28

30, 31

Name

nQA0, QA0

nOEA

DDA

nBYPASS

REF_CLK

GND

XTAL_OUT,

XTAL_IN

FSELB0,

FSELB1

FSELA0,

FSELA1

REF_SEL

QB0, nQB0

nOEB

nQB1, QB1

nQA1, QA1

Output

Power

Input

Unused

Power

Input

Power

Input

Output

Input

Output

Pulldown

Pullup

Pulldown

Type

Description

Bank A differential clock output pair. CML interface levels.

Core supply pins.

Output enable pin for Bank A outputs. See Table 3E for function.

LVCMOS/LVTTL interface levels.

Do not connect.

Analog supply pin.

PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels.

Single-ended reference clock input. LVCMOS/LVTTL interface levels.

Power supply ground.

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

Output frequency divider select enable pins for Bank B outputs.

See Table 3C for function. LVCMOS/LVTTL interface levels.

Output frequency divider select enable pins for Bank A outputs.

See Table 3B for function. LVCMOS/LVTTL interface levels.

PLL reference clock select pin. See Table 3A for function.

LVCMOS/LVTTL interface levels.

Bank B differential clock output pair. CML interface levels.

Output enable pin for Bank B outputs. See Table 3F for function.

LVCMOS/LVTTL interface levels.

Bank B differential clock output pair. CML interface levels.

Bank A differential clock output pair. CML interface levels.

NOTE:

Pulldown

and

Pullup

refer to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

nBYPASS,

REF_SEL,

nOEA, nOEB,

FSELB0, FSELB1,

FSELA0, FSELA1

Test Conditions

Minimum

Typical

Maximum

Units

Input

Capacitance

PULLDOWN

PULLUP

Input Pulldown Resistor

Input Pullup Resistor

k

REVISION B 07/20/15

FEMTOCLOCK

CRYSTAL-TO-CML CLOCK GENERATOR

845264 DATA SHEET

Function Tables

Table 3A. PLL Reference Clock Select Function Table

Input

REF_SEL

0 (default)

Operation

The crystal interface is the selected reference clock.

The REF_CLK input is the selected reference clock.

NOTE: REF_SEL is an asynchronous control.

Table 3B. FSELA[1:0] Output Divider Select Function Table

Input

FSELA1

0 (default)

FSELA0

0 (default)

Operation

÷2

÷4

÷5

÷ 10

Output Frequency

312.5MHz

156.25MHz

125MHz

62.5MHz

NOTE: FSELA[1:0] are asynchronous controls. Using 25MHz input reference.

Table 3C. FSELB[1:0] Output Divider Select Function Table

Input

FSELB1

0 (default)

FSELB0

0 (default)

Operation

÷2

÷4

÷5

÷ 10

Output Frequency

312.5MHz

156.25MHz

125MHz

62.5MHz

NOTE: FSELB[1:0] are asynchronous controls. Using 25MHz input reference.

REVISION B 07/20/15

FEMTOCLOCK

CRYSTAL-TO-CML CLOCK GENERATOR

845264 DATA SHEET

Table 3D. PLL nBYPASS Function Table

Input

nBYPASS

1 (default)

Operation

PLL is bypassed. The reference frequency f

REF

is divided by the selected

output divider. AC specifications do not apply in PLL bypass mode.

PLL is enabled. The reference frequency f

REF

is multiplied by the selected

feedback divider and then divided by the selected output divider.

NOTE: nBYPASS is an asynchronous control.

Table 3E. Output Enable Function Table

Input

nOEA

0 (default)

Operation

QA[1:0], nQA[1:0] Outputs enabled.

QA[1:0], nQA[1:0] Outputs disabled (high-impedance).

NOTE: nOEA is an asynchronous control.

Table 3F. Output Enable Function Table

Input

nOEB

0 (default)

Operation

QB[1:0], nQB[1:0] Outputs enabled.

QB[1:0], nQB[1:0] Outputs disabled (high-impedance).

NOTE: nOEB is an asynchronous control.

REVISION B 07/20/15

FEMTOCLOCK

CRYSTAL-TO-CML CLOCK GENERATOR

845264 DATA SHEET

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the

DC Characteristics or AC

Characteristics

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

XTAL_IN

Other Inputs

Outputs, I

Package Thermal Impedance,



Storage Temperature, T

STG

Rating

4.6V

0V to V

-0.5V to V

+ 0.5V

-0.5V to V

+ 0.5V

43.4°C/W (0 mps)

-65C to 150C

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics,

= 3.3V±5%, T

= -40°C to 85°C

Symbol

DDA

Parameter

Core Supply Voltage

Analog Supply Voltage

Power Supply Current

Analog Supply Current

Test Conditions

Minimum

3.135

– 0.12

Typical

3.3

Maximum

3.465

Units

Table 4B. Power Supply DC Characteristics,

= 2.5V±5%, T

= -40°C to 85°C

Symbol

DDA

Parameter

Core Supply Voltage

Analog Supply Voltage

Power Supply Current

Analog Supply Current

Test Conditions

Minimum

2.375

– 0.11

Typical

2.5

Maximum

2.625

Units

REVISION B 07/20/15

FEMTOCLOCK

CRYSTAL-TO-CML CLOCK GENERATOR

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845264AKILFT Related Products

	845264AKILFT	845264AKILF
Description	VFQFPN-32, Reel	VFQFPN-32, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN	VFQFPN
package instruction	VFQFN-32	VFQFN-32
Contacts	32	32
Manufacturer packaging code	NLG32P1	NLG32P1
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Other features	ALSO OPERTES AT 3.3V SUPPLY	ALSO OPERTES AT 3.3V SUPPLY
JESD-30 code	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e3	e3
length	5 mm	5 mm
Humidity sensitivity level	3	3
Number of terminals	32	32
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	312.5 MHz	312.5 MHz
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
Master clock/crystal nominal frequency	25 MHz	25 MHz
Maximum seat height	1 mm	1 mm
Maximum supply voltage	2.625 V	2.625 V
Minimum supply voltage	2.375 V	2.375 V
Nominal supply voltage	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin (Sn)	Tin (Sn)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	5 mm	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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