FemtoClock
®
Crystal/LVCMOS-to-
LVCMOS/LVTTL Frequency Synthesizer
840024I
DATA SHEET
General Description
The
840024I
is a four output LVCMOS/LVTTL
Synthesizer
optimized
to generate Ethernet reference clock frequency. The
840024I
uses
IDT’s
3
RD
generation low phase noise VCO technology and can
achieve 1ps or lower typical random RMS phase jitter, easily meeting
Ethernet jitter requirements. The
840024I
is packaged in a small
20-pin TSSOP package.
Features
•
•
•
•
•
Four LVCMOS / LVTTL outputs
Selectable
crystal oscillator interface or LVCMOS / LVTTL
single-ended clock input
Supports
the following output frequency: 125MHz
RMS phase jitter @125MHz (1.875MHz - 20MHz):
0.6ps (typical)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to
85°C
ambient operating temperature
Available in lead-free (RoHS 6) package
•
•
Block Diagram
OE
nPLL_SEL
Pullup
Pulldown
Pin Assignment
nc
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Q0
nXTAL_SEL
XTAL_IN
25MHz
Pulldown
1
Q1
OSC
XTAL_OUT
TEST_CLK
Pulldown
0
Phase
Detector
VCO
0
N = ÷5
Q2
1
M =
÷
25 (fixed)
Q3
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
MR
Pulldown
840024I Rev C 4/3/15
1
©2015 Integrated Device Technology, Inc.
840024I DATA SHEET
Table 1. Pin Descriptions
Number
1, 2,
9,
20
3
4
5
6
7
8
10
11, 12
13, 19
14, 15, 17, 18
16
Name
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2, Q1,
Q0
V
DDO
Unused
Input
Input
Input
Input
Input
Power
Power
Input
Power
Output
Power
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Type
Description
No connect pins.
PLL reference select control input.
See
Table
3A.
LVCMOS/LVTTL interface levels.
Single-ended
clock input. LVCMOS/LVTTL interface levels.
Output enable control pin.
See
Table
3B.
LVCMOS/LVTTL interface levels.
Master reset control pin.
See
Table
3C.
LVCMOS/LVTTL interface levels.
PLL bypass control input.
See
Table
3D.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply ground.
Single-ended
clock outputs. 17
output impedance.
LVCMOS/LVTTL interface levels.
Output supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors.
See
Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
=
3.3V
± 5%
V
DDO
= 2.5V ± 5%
Test Conditions
Minimum
Typical
4
8
51
51
17
21
Maximum
Units
pF
pF
k
k
Rev C 4/3/15
2
FEMTOCLOCK® CRYSTAL/LVCMOS-TO- LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
840024I DATA SHEET
Function Tables
Table 3A. nXTAL_SEL PLL Reference Select Function Table
nXTAL_SEL
0 (default)
1
PLL Reference Input
XTAL Interface
TEST_CLK
Table 3B. Output Enable Function Table
OE
0
1 (default)
Output Operation
Q[0:3] are disabled in high-impedance state.
Q[0:3] are enabled.
Table 3C. Master Reset Function Table
MR
0 (default)
1
Reset Operation
Normal operation, internal dividers are enabled.
Internal dividers are reset, Q[0:3] are disabled in logic low state.
Table 3D. PLL Bypass Function Table
nPLL_SEL
0 (default)
1
PLL Operation
PLL is enabled
PLL is bypassed. The output frequency is equal to the selected
reference frequency divided by the output divider of 5.
Rev C 4/3/15
3
FEMTOCLOCK® CRYSTAL/LVCMOS-TO- LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
840024I DATA SHEET
Absolute Maximum Ratings
NOTE:
Stresses
beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply
Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage
Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
86.7C/W
(0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
=
3.3V±5%
, T
A
= -40°C to
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core
Supply
Voltage
Analog
Supply
Voltage
Output
Supply
Voltage
Core
Supply
Current
Analog
Supply
Current
Output
Supply
Current
No Load
Test Conditions
Minimum
3.135
V
DD
– 0.14
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
90
14
8
Units
V
V
V
mA
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
=
3.3V±5%,
V
DDO
= 2.5V±5%, T
A
= -40°C to
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core
Supply
Voltage
Analog
Supply
Voltage
Output
Supply
Voltage
Core
Supply
Current
Analog
Supply
Current
Output
Supply
Current
No Load
Test Conditions
Minimum
3.135
V
DD
– 0.14
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
90
14
8
Units
V
V
V
mA
mA
mA
Table 4C. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C to
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Rev C 4/3/15
Parameter
Core
Supply
Voltage
Analog
Supply
Voltage
Output
Supply
Voltage
Core
Supply
Current
Analog
Supply
Current
Output
Supply
Current
No Load
4
Test Conditions
Minimum
2.375
V
DD
– 0.14
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
90
14
8
Units
V
V
V
mA
mA
mA
FEMTOCLOCK® CRYSTAL/LVCMOS-TO- LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
840024I DATA SHEET
Table 4D. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to
85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
=
3.465V
V
DD
= 2.625V
Input Low Voltage
OE
I
IH
Input
High Current
TEST_CLK, MR,
nXTAL_SEL,
nPLL_SEL
OE
I
IL
Input
Low Current
TEST_CLK, MR,
nXTAL_SEL,
nPLL_SEL
V
DD
=
3.465V
V
DD
= 2.625V
V
DD
= V
IN
=
3.465V
or 2.625V
V
DD
= V
IN
=
3.465V
or 2.625V
V
DD
=
3.465V
or 2.625V,
V
IN
= 0V
V
DD
=
3.465V
or 2.625V,
V
IN
= 0V
V
DDO
=
3.3V
± 5%; I
OH
= -12mA
V
DDO
= 2.5V ± 5%; I
OH
= -12mA
Output Low Voltage
V
DDO
=
3.3V
± 5% or 2.5V ± 5%;
I
OL
= 12mA
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
150
Units
V
V
V
V
µA
µA
V
IL
-150
µA
-5
2.6
1.8
0.5
µA
V
V
V
V
OH
V
OL
Output High Voltage
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent
Series
Resistance (ESR)
Shunt
Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
Rev C 4/3/15
5
FEMTOCLOCK® CRYSTAL/LVCMOS-TO- LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
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