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A1460A-2PGG207C

Description
Field Programmable Gate Array, 848 CLBs, 6000 Gates, 150MHz, CMOS, CPGA207, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, PGA-207
CategoryProgrammable logic devices    Programmable logic   
File Size4MB,90 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
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A1460A-2PGG207C Overview

Field Programmable Gate Array, 848 CLBs, 6000 Gates, 150MHz, CMOS, CPGA207, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, PGA-207

A1460A-2PGG207C Parametric

Parameter NameAttribute value
MakerMicrosemi
package instructionHPGA,
Reach Compliance Codeunknown
maximum clock frequency150 MHz
Combined latency of CLB-Max2.3 ns
JESD-30 codeS-CPGA-P207
length44.958 mm
Configurable number of logic blocks848
Equivalent number of gates6000
Number of terminals207
Maximum operating temperature70 °C
Minimum operating temperature
organize848 CLBS, 6000 GATES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeHPGA
Package shapeSQUARE
Package formGRID ARRAY, HEAT SINK/SLUG
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Maximum seat height9.4234 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width44.958 mm
Revision 3
Accelerator Series FPGAs – ACT 3 Family
Features
• Up to 10,000 Gate Array Equivalent Gates (up to 25,000
equivalent PLD Gates)
• Highly Predictable Performance with 100% Automatic Place-
and-Route
• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)
• Up to 186 MHz On-Chip Performance (–1 Speed Grade)
• Up to 228 User-Programmable I/O Pins
• Four Fast, Low-Skew Clock Networks
Table 1 • ACT 3 Family Product Information
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package (40 gates)
20-Pin PAL Equivalent Packages (100 gates)
Logic Modules
S-Module
C-Module
Dedicated Flip-Flops
1
User I/Os (maximum)
Chip-to-Chip
3
(MHz)
Accumulators (16-bit, MHz)
Loadable Counter (16-bit, MHz)
Prescaled Loadable Counters (16-bit, MHz)
Datapath, Shift Registers (MHz)
Clock-to-Output (pad-to-pad, ns)
Packages
4
(by pin count)
CPGA
PLCC
PQFP
RQFP
VQFP
TQFP
BGA
CQFP
PG100
5
PL84
PQ100
VQ100
PG133
5
PL84
PQ100, PQ160
VQ100
CQ132
PG175
5
PL84
PQ160
VQ100
TQ176
PG207
PQ160, PQ208
TQ176
BG225
5
CQ196
PG257
RQ208
BG313
CQ256
1,500
3,750
40
15
200
104
96
264
80
80
47
82
186
186
9.0
2,500
6,250
60
25
310
160
150
360
100
80
47
82
186
186
9.0
4,000
10,000
100
40
564
288
276
568
140
80
47
82
186
186
9.5
6,000
15,000
150
60
848
432
416
768
168
78
47
82
150
150
10.0
10,000
25,000
250
100
1,377
697
680
1,153
228
76
47
78
150
150
10.5
A1415
A1425
A1440
A1460
A14100
More than 500 Macro Functions
Replaces up to Twenty 32 Macro-Cell CPLDs
Replaces up to One Hundred 20-Pin PAL
®
Packages
Up to 1,153 Dedicated Flip-Flops
VQFP, TQFP, BGA, and PQFP Packages
Nonvolatile, User Programmable
Fully Tested Prior to Shipment
5.0 V and 3.3 V Versions
Optimized for Logic Synthesis Methodologies
Low Power CMOS Technology
Maximum Performance
2
(worst-case commercial, –1 speed grade)
Notes:
1. One flip-flop per S0Module, two flip-flops per I/O Module.
2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.
3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the
"System Performance Model" on page 1-1
and
Table 1-1 on page 1-2.
4. See the
"Product Plan" table on page III
for package availability.
5. Discontinued device and package combination.
6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product
Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:
PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004
January 2012
© 2012 Microsemi Corporation
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