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CAT25C256U20

Description
EEPROM, 32KX8, Serial, CMOS, PDSO20, TSSOP-20
Categorystorage    storage   
File Size66KB,11 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT25C256U20 Overview

EEPROM, 32KX8, Serial, CMOS, PDSO20, TSSOP-20

CAT25C256U20 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCatalyst
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts20
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum clock frequency (fCLK)2 MHz
JESD-30 codeR-PDSO-G20
JESD-609 codee0
length6.5 mm
memory density262144 bit
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals20
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/SerialSERIAL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height1.1 mm
Serial bus typeSPI
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
Maximum write cycle time (tWC)10 ms
Main Menu
CAT25C128/256
128K/256K-Bit SPI Serial CMOS E
2
PROM
FEATURES
s
5 MHz SPI Compatible
s
1.8 to 6.0 Volt Operation
s
Hardware and Software Protection
s
Zero Standby Current
s
Low Power CMOS Technology
s
SPI Modes (0,0 &1,1)
s
Commercial, Industrial and Automotive
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Self-Timed Write Cycle
s
8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
s
64-Byte Page Write Buffer
s
Block Write Protection
Temperature Ranges
– Protect 1/4, 1/2 or all of E
2
PROM Array
DESCRIPTION
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS E
2
PROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology substan-
tially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The
HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C128/
256 is designed with software and hardware write pro-
tection features including Block Lock protection. The
device is available in 8-pin DIP, 8-pin SOIC, 16-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
PIN CONFIGURATION
SOIC Package (S, K) TSSOP Package (U14)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
BLOCK DIAGRAM
DIP Package (P)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SENSE AMPS
SHIFT REGISTERS
SOIC Package (S16)
CS
SO
NC
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
HOLD
NC
NC
NC
NC
SCK
SI
CS
SO
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
TSSOP Package (U20)
NC
CS
SO
SO
NC
NC
WP
V
SS
NC
NC
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
VCC
HOLD
HOLD
NC
NC
SCK
SI
NC
NC
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
XDEC
E
2
PROM
ARRAY
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
STATUS
REGISTER
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
25C128 F02
Note: CAT25C256 not available in 8-Lead S or U packages.
Doc. No. 25088-00 1/01
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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