X25256V20I-2.5 datasheet, PDF - EEWORLD Datasheet

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X25256V20I-2.5: DescriptionEEPROM, 32KX8, Serial, CMOS, PDSO20, PLASTIC, TSSOP-20; Categorystorage storage; File Size485KB，17 Pages; ManufacturerIC Microsystems Sdn Bhd

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X25256V20I-2.5 Overview

EEPROM, 32KX8, Serial, CMOS, PDSO20, PLASTIC, TSSOP-20

X25256V20I-2.5 Parametric

Parameter Name	Attribute value
Maker	IC Microsystems Sdn Bhd
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	20
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum clock frequency (fCLK)	5 MHz
JESD-30 code	R-PDSO-G20
length	6.5 mm
memory density	262144 bit
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	20
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	SERIAL
Certification status	Not Qualified
Maximum seat height	1.2 mm
Serial bus type	SPI
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm
Maximum write cycle time (tWC)	10 ms

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This X25256 device has been acquired by

IC MICROSYSTEMS from Xicor; Inc.

Preliminary Information

256K

X25256

5MHz SPI Serial E

PROM with Block Lock

™

32K x 8 Bit

Protection

FEATURES

•5MHz Clock Rate

•Low Power CMOS

—<1µA standby current

—<5mA active current

•2.5V To 5.5V Power Supply

•SPI Modes (0,0 & 1,1)

•32K X 8 Bits

—64 byte page mode

•Block Lock

™

Protection

—Protect first page, first 2 pages, first 4 pages,

first 8 pages, 1/4, 1/2 or all of E

2PROM

array

•Programmable Hardware Write Protection

•Packages —8-

lead XBGA

—8-lead SOIC (JEDEC, EIAJ)

—20-lead TSSOP

DESCRIPTION

The X25256 is a CMOS 256K-bit serial E

PROM, inter-

nally organized as 32K x 8. The X25256 features a

Serial Peripheral Interface (SPI) and software protocol

allowing operation on a simple three-wire bus. The bus

signals are a clock input (SCK) plus separate data in

(SI) and data out (SO) lines. Access to the device is

controlled through a chip select (CS) input, allowing any

—In-circuit programmable ROM mode

•Built-In Inadvertent Write Protection

—Power-up/down protection circuitry

—Write enable latch

number of devices to share the same bus.

The X25256 also features two additional inputs that

provide the end user with added flexibility. By asserting

the HOLD input, the X25256 will ignore transitions on its

inputs, thus allowing the host to service higher priority

interrupts. The WP input can be used as a hardwire

input to the X25256 disabling all write attempts to the

status register, thus providing a mechanism for limiting

end user capability of altering first page, first 2 pages, 4

—Write protect pin

•Self-Timed Write Cycle

—5ms write cycle time (typical)

•High Reliability

—Endurance: 100,000 cycles

—Data Retention: 100 Years

—ESD protection: 2000V on all pins

pages, 8 pages, 0, 1/4, 1/2 or all of the memory.

FUNCTIONAL DIAGRAM

Status

Write

Protect

32K Byte

Array

Logic

128

128 X 512

SCK

Command

Decode

HOLD

And

Control

Logic

X-Decode

Protect

128

128 X 512

Logic

248

248 X 512

256 X 512

4 X 512

2 X 512

1 X 512

Write

Control

And

Timing

Logic

Y Decode

Data Register

™

and Block Lock

™

Protection is a trademark of Xicor, Inc.

www.icmic.com

Characteristics subject to change without notice.

1 of 17

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