This X76F400 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmic
IC MICROSYSTEMS
TM
4K
X76F400
Secure SerialFlash
DESCRIPTION
512 x 8 bit
FEATURES
•64-bit password security
•One array (496 bytes) two passwords (16 bytes)
—Read password
—Write password
•Programmable passwords
•Retry counter register
—Allows 8 tries before clearing of the array
•32-bit response to reset (RST input)
•8 byte sector write mode
•1MHz clock rate
•2-wire serial interface
•Low power CMOS
—2.5 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
•High reliability endurance:
—100,000 write cycles
•Data retention: 100 years
•Available in:
The X76F400 is a password access security supervisor,
containing one 3968-bit Secure Serial Flash array.
Access to the memory array can be controlled by two 64-bit
passwords. These passwords protect read and
write operations of the memory array.
The X76F400 features a serial interface and software
protocol allowing operation on a popular 2-wire bus.
The bus signals are a clock input (SCL) and a bi-directional
data input and output (SDA).
The X76F400 also features a synchronous response to
reset, providing an automatic output of a hard-wired
32-bit data stream, thereby meeting the industry standard
for memory cards.
The X76F400 utilizes Xicor’s proprietary Direct Write
™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
—8-lead, SOIC,TSSOP
BLOCK DIAGRAM
Retry Counter
Data Transfer
Array Access
Enable
SCL
SDA
Interface
Logic
Erase Logic
496 Byte
EEPROM Array
Password Array
and Password
Verification Logic
RST
ISO Reset
Response Register
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Characteristics subject to change without notice.
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X76F400
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
If the X76F400 is in a nonvolatile write cycle a “no ACK”
(SDA = High) response will be issued in
response to loading of the command byte. If a stop is issued
prior to the nonvolatile write cycle, the write
operation will be terminated; the part will then reset and
enter into a standby mode.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. During a
read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
(The basic sequence is illustrated in Figure 1.)
PIN NAMES
Symbol
SDA
SCL
RST
V
CC
V
SS
NC
Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
Reset (RST)
RST is a device reset pin. When RST is pulsed high, the
X76F400 will output 32 bits of fixed data, which
conforms to the standard for “synchronous response-
to-reset.” The part must not be in a write cycle for the
response-to-reset to occur. See Figure 7. If power is
interrupted during the response-to-reset, the response-
to-reset will be aborted and the part will return to the
standby state. The response to reset is “mask
PIN CONFIGURATION
SOIC
programmable” only!
DEVICE OPERATION
The X76F400 memory array consists of 62 8-byte sectors.
Read or write access to the array always begins at
the first address of the sector. Read operations then can
continue indefinitely. Write operations must total 8 bytes.
V
SS
1
2
3
4
TSSOP
8
7
6
5
V
CC
NC
SDA
NC
RST
SCL
NC
There are two primary modes of operation for the
X76F400; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8- byte
passwords.
The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0.’
The user must perform ACK polling to determine the
validity of the password, prior to starting a data transfer
(see Acknowledge Polling). Only after the correct password
is accepted, and an ACK polling has been
V
CC
1
2
3
4
8
7
6
5
RST
SCL
SDA
NC
NC
NC
V
SS
After each transaction is completed, the X76F400 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
performed, can the data transfer occur. See Figure 1.
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “response-to-reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
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X76F400
Figure 1. X76F400 Device Operation
Load Command/Address Byte
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer to
Figures 2 and 3.
Load 8-Byte
Password
Start Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F400 continuously monitors the SDA and
SCL lines for the start condition, and will not
Verify Password
Acceptance by
Use of ACK Polling
respond to any command until this condition is met.
Read/Write
Data Bytes
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or write
command. Because of the push/pull output, a
Retry Counter
The X76F400 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
start cannot be generated while the part is outputting data.
Starts are inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also used
to reset the device during a command or data
before any action is taken. The counter will increment with
any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of the
passwords are cleared to “0.” If a correct password
is received prior to retry counter overflow, the retry
counter is reset and access is granted.
input sequence, leaving the device in the standby
power mode. As with starts, stops are inhibited when
Device Protocol
The X76F400 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the slave.
The master will always initiate data transfers and
outputting data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle the receiver will pull
provide the clock for both transmit and receive operations.
Therefore, the X76F400 will be considered a
the SDA line LOW to acknowledge that it received the 8
bits of data.
The X76F400 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F400 will respond with an acknowl-
slave in all applications.
edge after the receipt of each subsequent 8-bit word.
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
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X76F400
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
START Condition
STOP Condition
Table 1. X76F400 Instruction Set
Command After Start
1 S
5
S
4
S
3
S
2
S
1
S
0
0
1 S
5
S
4
S
3
S
2
S
1
S
0
1
11111100
11111110
01010101
Command Description
Sector Write
Sector Read
Change Write Password
Change Read Password
Password ACK Command
Password Used
Write
Read
Write
Write
None
Illegal command codes will be disregarded. The part will
respond with a “no-ACK” to the illegal byte and
then return to the standby mode. All write/read operations
require a password.
with the nonvolatile write operation, it will issue a “no-
ACK” in response. If the nonvolatile write operation is
completed, an “ACK” will be returned and the host can then
proceed with the rest of the protocol.
Data ACK Polling Sequence
Write Sequence
Completed Enter ACK
PROGRAM OPERATIONS
Sector Write
The sector write mode requires issuing the 8-bit write
command followed by the password and then the data
bytes transferred as illustrated in Figure 4. The write
command byte contains the address of the sector to be
Polling
written. Data is written starting at the first address of a
sector and 8 bytes must be transferred. After the last
byte to be transferred is acknowledged, a stop condition is
issued which starts the nonvolatile write cycle. If
more or less than 8 bytes are transferred, the data in the
sector remains unchanged.
Issue START
Issue New
Command Code
ACK Polling
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F400 initiates the
internal nonvolatile write cycle. In order to take advantage of
the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start condition
followed by the new command code of 8 bits
ACK
Returned?
YES
PROCEED
NO
(first byte of the protocol). If the X76F400 is still busy
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X76F400
After the password sequence, there is always a nonvola- tile
write cycle. This is done to discourage random
guesses of the password if the device is being tampered with.
In order to continue the transaction, the X76F400
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
with regular acknowledge polling the user can either time
out for 10ms and then issue the ACK polling once,
READ OPERATIONS
Read operations are initiated in the same manner as
write operations but with a different command code.
Sector Read
With sector read, a sector address is supplied with the read
command. Once the password has been
acknowledged data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A
read operation always begins at the first byte in the
sector, but may stop at any time. Random accesses to
the array are not possible. Continuous reading from the
array will return data from successive sectors. After
reading the last sector in the array, the address is auto-
matically set to the first sector in the array and data can
continue to be read out. After the last bit has been read,
a stop condition is generated without sending a
or continuously loop as described in the flow.
If the password inserted is correct, the nonvolatile cycle
in response to the password ACK polling
sequence is over, and an “ACK” is returned.
If the password inserted is incorrect, a “no ACK” is
returned, even if the nonvolatile cycle is over. There-
fore, the user cannot be certain that the password is
incorrect until the 10ms write cycle time has elapsed.
Password ACK Polling Sequence
preceding acknowledge.
Password Load
Completed Enter ACK
Polling
Issue START
Issue Password
ACK Command
ACK
Returned?
YES
PROCEED
NO
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Characteristics subject to change without notice.
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