MPC8306VMAFFCA datasheet, PDF - EEWORLD Datasheet

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MPC8306VMAFFCA: Description32-BIT, 333MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369; CategoryThe embedded processor and controller Microcontrollers and processors; File Size430KB，74 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MPC8306VMAFFCA Overview

32-BIT, 333MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369

MPC8306VMAFFCA Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	LFBGA,
Contacts	369
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width
bit size	32
boundary scan	YES
maximum clock frequency	66.67 MHz
External data bus width
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B369
JESD-609 code	e1
length	19 mm
low power mode	YES
Number of terminals	369
Maximum operating temperature	105 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Maximum seat height	1.61 mm
speed	333 MHz
Nominal supply voltage	1 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	19 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Freescale Semiconductor

Technical Data

Document Number:MPC8306EC

Rev. 2, 09/2011

MPC8306

PowerQUICC II Pro Integrated

Communications Processor

Family Hardware Specifications

This document provides an overview of the

MPC8306

PowerQUICC II Pro

processor features. The MPC8306 is a

cost-effective, highly integrated communications processor

that addresses the requirements of several networking

applications, including residential gateways,

modem/routers, industrial control, and test and measurement

applications. The MPC8306 extends current PowerQUICC

offerings, adding higher CPU performance, additional

functionality, and faster interfaces, while addressing the

requirements related to time-to-market, price, power

consumption, and board real estate. This document describes

the electrical characteristics of MPC8306.

To locate published errata or updates for this document, refer

to the MPC8306 product summary page on our website

listed on the back cover of this document or contact your

local Freescale sales office.

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Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 12

DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ethernet and MII Management . . . . . . . . . . . . . . . . . 21

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

eSDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 48

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

System Design Information . . . . . . . . . . . . . . . . . . . 68

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 71

Document Revision History . . . . . . . . . . . . . . . . . . . 73

Overview

In summary, the MPC8306 provides users with a highly integrated, fully programmable communications

processor. This helps to ensure that a low-cost system solution can be quickly developed and offers

flexibility to accommodate new standards and evolving system requirements.

1.1

Features

The major features of the device are as follows:

• e300c3 Power Architecture processor core

— Enhanced version of the MPC603e core

— High-performance, superscalar processor core with a four-stage pipeline and low interrupt

latency times

— Floating-point, dual integer units, load/store, system register, and branch processing units

— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities

— Dynamic power management

— Enhanced hardware program debug features

— Software-compatible with Freescale processor families implementing Power Architecture

technology

— Separate PLL that is clocked by the system bus clock

— Performance monitor

• QUICC Engine block

— 32-bit RISC controller for flexible support of the communications peripherals with the

following features:

– One clock per instruction

– Separate PLL for operating frequency that is independent of system’s bus and e300 core

frequency for power and performance optimization

– 32-bit instruction object code

– Executes code from internal IRAM

– 32-bit arithmetic logic unit (ALU) data path

– Modular architecture allowing for easy functional enhancements

– Slave bus for CPU access of registers and multiuser RAM space

– 48 Kbytes of instruction RAM

– 16 Kbytes of multiuser data RAM

– Serial DMA channel for receive and transmit on all serial channels

— Five unified communication controllers (UCCs) supporting the following protocols and

interfaces:

– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.

– IEEE Std. 1588™ support

– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)

– HDLC Bus (bit rate up to 10 Mbps)

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2

Freescale Semiconductor

MPC8306VMAFFCA Related Products

	MPC8306VMAFFCA	MPC8306VMABFCA	MPC8306CVMABFCA	MPC8306CVMAFFCA	MPC8306CVMADFCA	MPC8306VMADFCA	MPC8306CVMACFCA
Description	32-BIT, 333MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369	32-BIT, 133MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369	32-BIT, 133MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369	32-BIT, 333MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369	32-BIT, 266MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369	32-BIT, 266MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369	32-BIT, 200MHz, RISC PROCESSOR, PBGA369, 19 MM X 19 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-369
Maker	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LFBGA,	LFBGA,	LFBGA,	LFBGA,	LFBGA,	LFBGA,	LFBGA,
Contacts	369	369	369	369	369	369	369
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
bit size	32	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	66.67 MHz	66.67 MHz	66.67 MHz	66.67 MHz	66.67 MHz	66.67 MHz	66.67 MHz
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-PBGA-B369	S-PBGA-B369	S-PBGA-B369	S-PBGA-B369	S-PBGA-B369	S-PBGA-B369	S-PBGA-B369
JESD-609 code	e1	e1	e1	e1	e1	e1	e1
length	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm
low power mode	YES	YES	YES	YES	YES	YES	YES
Number of terminals	369	369	369	369	369	369	369
Maximum operating temperature	105 °C	105 °C	105 °C	105 °C	105 °C	105 °C	105 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Maximum seat height	1.61 mm	1.61 mm	1.61 mm	1.61 mm	1.61 mm	1.61 mm	1.61 mm
speed	333 MHz	133 MHz	133 MHz	333 MHz	266 MHz	266 MHz	200 MHz
Nominal supply voltage	1 V	1 V	1 V	1 V	1 V	1 V	1 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal surface	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm	19 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC

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