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XC2C64 CoolRunner-II CPLD
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0
DS092 (v3.0) November 30, 2005
Product Specification
·
100% product term routability across function
block
Note: This product is being discontinued.
You cannot
order this part after April 24, 2006. Xilinx recommends
replacing the XC2C64 device with the XC2C64A device in
all designs as soon as possible. The XC2C64A device is
pin-to-pin compatible with the XC2C64 device. See
XCN05017
for details regarding the discontinuation of the
XC2C64 device.
-
Hot pluggable
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
Features
•
Optimized for 1.8V systems
- As fast as 4.6 ns pin-to-pin logic delays
- As low as 15
µA
quiescent current
Industries best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
Available in multiple package options
- 44-pin PLCC with 33 user I/O
- 44-pin VQFP with 33 user I/O
- 56-ball CP BGA with 45 user I/O
- 100-pin VQFP with 64 user I/O
Advanced system features
- Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- RealDigital™ 100% CMOS product term
generation
- Flexible clocking modes
·
Optional DualEDGE triggered registers
- Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state or weak pull-up on
selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
·
Superior pinout retention
•
•
•
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS092 (v3.0) November 30, 2005
Product Specification
www.xilinx.com
1
XC2C64 CoolRunner-II CPLD
LVCMOS33 (see
Table 1).
This device is also LVCOMOS15
compatible with the use of Schmitt-trigger inputs.
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RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital, a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high performance and
low power operation.
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt-trigger inputs.
Table 1:
I/O Standards for XC2C64
IOSTANDARD Output
Attribute
V
CCIO
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
(1)
3.3
3.3
2.5
1.8
1.5
Input
V
CCIO
3.3
3.3
2.5
1.8
1.5
Board
Input Termination
V
REF
Voltage V
T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
Table 1
for I/O stan-
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
20
(1) Requires Schmitt-trigger inputs.
15
I
CC
(mA)
10
5
0
0
50
100
150
200
250
Frequency (MHz)
DS092_01_092302
Figure 1:
I
CC
vs Frequency
Table 2:
I
CC
vs Frequency (LVCMOS 1.8V T
A
= 25°C)
(1)
Frequency (MHz)
0
Typical I
CC
(mA)
0.015
25
1.8
50
3.7
75
5.5
100
7.48
150
11.0
175
12.7
200
14.6
225
15.3
240
17.77
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
2
www.xilinx.com
DS092 (v3.0) November 30, 2005
Product Specification
R
XC2C64 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
CCIO
V
JTAG(2)
V
AUX
V
IN(1)
V
TS(1)
V
STG(3)
T
J
Description
Supply voltage relative to ground
Supply voltage for output drivers
JTAG input voltage limits
JTAG input supply voltage
Input voltage relative to ground
Voltage applied to 3-state output
Storage Temperature (ambient)
Junction Temperature
Value
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–65 to +150
+150
Units
V
V
V
V
V
V
°C
°C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the
Device Packaging
information on the Xilinx website. For Pb free
packages, see
XAPP427.
Recommended Operating Conditions
Symbol
V
CC
V
CCIO
Parameter
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0°C to +70°C
Industrial T
A
= –40°C to +85°C
Min
1.7
1.7
3.0
2.3
1.7
1.4
1.7
Max
1.9
1.9
3.6
2.7
1.9
1.6
3.6
Units
V
V
V
V
V
V
V
Supply voltage for output drivers @ 3.3V operation
Supply voltage for output drivers @ 2.5V operation
Supply voltage for output drivers @ 1.8V operation
Supply voltage for output drivers @ 1.5V operation
V
AUX
JTAG programming pins
DC Electrical Characteristics
(Over Recommended Operating Conditions)
Symbol
I
CCSB
I
CCSB
I
CC(1)
C
JTAG
C
CLK
C
IO
I
IL(2)
I
IH(2)
Parameter
Standby current Commercial
Standby current Industrial
Dynamic current
JTAG input capacitance
Global clock input capacitance
I/O capacitance
Input leakage current
I/O High-Z leakage
Test Conditions
V
CC
= 1.9V, V
CCIO
= 3.6V
V
CC
= 1.9V, V
CCIO
= 3.6V
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
V
IN
= 0V or V
CCIO
to 3.9V
V
IN
= 0V or V
CCIO
to 3.9V
Typical
Max.
100
165
500
5
10
12
10
+/-1
+/-1
Units
µA
µA
µA
mA
pF
pF
pF
µA
µA
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at
V
CC
=V
CCIO
= 1.9V.
2. See Quality and Reliability section of the CoolRunner-II family data sheet.
DS092 (v3.0) November 30, 2005
Product Specification
www.xilinx.com
3
XC2C64 CoolRunner-II CPLD
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LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol
V
CCIO
V
IH
V
IL
V
OH
V
OL
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage
I
OH
= –8 mA, V
CCIO
= 3V
I
OH
= –0.1 mA, V
CCIO
= 3V
Low level output voltage
I
OL
= 8 mA, V
CCIO
= 3V
I
OL
= 0.1 mA, V
CCIO
= 3V
Test Conditions
Min.
3.0
2
–0.3
V
CCIO
– 0.4V
V
CCIO
– 0.2V
-
-
Max.
3.6
3.9
0.8
-
-
0.4
0.2
Units
V
V
V
V
V
V
V
LVCMOS 2.5V DC Voltage Specifications
Symbol
V
CCIO
V
IH
V
IL
V
OH
V
OL
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage
I
OH
= –8 mA, V
CCIO
= 2.3V
I
OH
= –0.1 mA, V
CCIO
= 2.3V
Low level output voltage
I
OL
= 8 mA, V
CCIO
= 2.3V
I
OL
= 0.1 mA, V
CCIO
= 2.3V
Test Conditions
Min.
2.3
1.7
–0.3
V
CCIO
– 0.4V
V
CCIO
– 0.2V
-
-
Max.
2.7
3.9
0.7
-
-
0.4
0.2
Units
V
V
V
V
V
V
V
4
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DS092 (v3.0) November 30, 2005
Product Specification
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XC2C64 CoolRunner-II CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol
V
CCIO
V
IH
V
IL
V
OH
V
OL
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage
I
OH
= –8 mA, V
CCIO
= 1.7V
I
OH
= –0.1 mA, V
CCIO
= 1.7V
Low level output voltage
I
OL
= 8 mA, V
CCIO
= 1.7V
I
OL
= 0.1 mA, V
CCIO
= 1.7V
Test Conditions
Min.
1.7
0.65 x V
CCIO
–0.3
V
CCIO
– 0.45
V
CCIO
– 0.2
-
-
Max.
1.9
3.9
0.35 x V
CCIO
-
-
0.45
0.2
Units
V
V
V
V
V
V
V
LVCMOS 1.5V DC Voltage Specifications
(1)
Symbol
V
CCIO
V
T+
V
T-
V
OH
V
OL
High level output voltage
I
OH
= –4 mA, V
CCIO
= 1.4V
I
OH
= –0.1 mA, V
CCIO
= 1.4V
Low level output voltage
I
OL
= 8 mA, V
CCIO
= 1.4V
I
OL
= 0.1 mA, V
CCIO
= 1.4V
Notes:
1. Hysteresis used on 1.5V inputs.
Parameter
Input source voltage
Input hysteresis threshold voltage
Test Conditions
Min.
1.4
0.5 x V
CCIO
0.2 x V
CCIO
V
CCIO
– 0.45
V
CCIO
– 0.2
-
-
Max.
1.6
0.8 x V
CCIO
0.5 x V
CCIO
-
-
0.4
0.2
Units
V
V
V
V
V
V
V
Schmitt Trigger Input DC Voltage Specifications
Symbol
V
CCIO
V
T+
V
T-
Parameter
Input source voltage
Input hysteresis threshold voltage
Test Conditions
Min.
1.4
0.5 x V
CCIO
0.2 x V
CCIO
Max.
3.9
0.8 x V
CCIO
0.5 x V
CCIO
Units
V
V
V
AC Electrical Characteristics Over Recommended Operating Conditions
-5
Symbol
T
PD1
T
PD2
T
SUD
T
SU1
T
SU2
T
HD
T
H
Parameter
Propagation delay single p-term
Propagation delay OR array
Direct input register clock setup time
Setup time (single p-term)
Setup time (OR array)
Direct input register hold time
P-term hold time
Min.
-
-
2.4
2.0
2.4
0
0
Max.
4.6
5.0
-
-
-
-
-
Min.
-
-
3.3
2.5
3.3
0
0
-7
Max.
6.7
7.5
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
DS092 (v3.0) November 30, 2005
Product Specification
www.xilinx.com
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