Model CB3 & CB3LV
HCMOS/TTL Clock Oscillator
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FEATURES
Standard 7.0mm x 5.0mm 4-Pad Surface Mount Package
HCMOS/TTL Compatible Output
Fundamental and 3
rd
Overtone Crystal Designs
Frequency Range 1 – 200 MHz
Frequency Stability ±50 ppm Standard, ±25 ppm and ±20 ppm Available
Operating Voltages +5.0Vdc or +3.3Vdc
Operating Temperature to -40°C to +85°C
Output Enable Standard
Tape & Reel Packaging
RoHS/Green Compliant (6/6)
APPLICATIONS
Applications for Model CB3 and CB3LV include digital video, networking equipment, wireless communications,
broadband access, Ethernet/Gigabit Ethernet, microprocessors/DSP/FPGA, storage area networks, fiber channel,
computers and peripherals, test and measurement, SONET/SDH/DWDM, base stations and Pico cells.
ORDERING INFORMATION
CB3
SUPPLY VOLTAGE
LV = +3.3Vdc
Blank = +5.0Vdc
FREQUENCY STABILITY
6 = ± 20 ppm
5 = ± 25 ppm
3 = ± 50 ppm [std]
1
-
-
M
FREQUENCY IN MHz
M - indicates MHz and decimal point.
3
7 = ± 32 ppm
2 = ± 100 ppm
2
2
OPERATING TEMPERATURE RANGE
C = -20°C to +70°C [standard]
I = -40°C to +85°C
1
1] 6I Stability/Temperature combination is not available.
2] These stabilities are not recommended for new designs.
3] Frequency is recorded with only leading significant digits before the ‘M’ and 4 - 6 significant digits after the ‘M’ (including zeros).
[Ex. 3.579545 MHz, code as 3M579545; 14.31818 MHz, code as 14M31818; 125 MHz, code as 125M0000]
4] CTS Distributors may add a -T or -1 at the end of the part number to indicate Tape and Reel packaging.
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
PACKAGING INFORMATION
[reference]
Device quantity is 1,000 pieces maximum per reel.
Document No. 008-0256-0
Page 1- 3
Rev. G
www.ctscorp.com
Model CB3 & CB3LV
7.0mm x 5.0mm Low Cost
HCMOS/TTL Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Storage Temperature
Frequency Range
CB3
CB3LV
Frequency Stability
Aging
Operating Temperature
Commercial
Industrial
Supply Voltage
CB3
CB3LV
Supply Current
CB3
I
CC
CB3LV
Δf/f
O
Δf
T
A
V
CC
±10%
Frequency Range
Tested load condition noted for typical values.
SYMBOL
V
CC
T
STG
f
O
CONDITIONS
-
-
-
-
See Note 1 and Ordering Information
First year
-
MIN
-0.5
-40
1.5
1.5
-
-
-20
-40
4.5
3.0
C
L
=50pF
C
L
=50pF
C
L
=15pF
C
L
=15pF
C
L
=15pF
C
L
=15pF
-
-
-
-
-
-
-
-
-
90%V
CC
V
CC
-0.6V
-
TYP
-
-
-
-
-
3
25
5.0
3.3
10
30
40
7
20
30
-
-
-
-
-
-
-
-
MAX
+7.0
+100
107
200
20,25,50 or 100
5
+70
+85
5.5
3.6
25
50
80
12
40
60
50
30
15
-
10%V
CC
0.4
-16/-8
+16/+8
55
UNIT
V
°C
MHz
± ppm
± ppm
°C
V
ELECTRICAL PARAMETERS
Output Load
Output Voltage Levels
Logic '1' Level
Logic '0' Level
Output Current
Logic '1' Level
Logic '0' Level
Output Duty Cycle
Rise and Fall Time
CB3
C
L
1.5MHz to 20MHz
20.001MHz to 80MHz
80.001MHz to 107MHz
1.5MHz to 20MHz
20.001MHz to 80MHz
80.001MHz to 200MHz
1.5MHz to 50MHz
50.001MHz to 80MHz
80.001MHz to 200MHz
CMOS Load
10 TTL LOAD
CMOS
TTL Load
V
OH
= 3.9V/2.2V
V
OL
= 0.4V
@ 50% Level
@ 10% - 90% Levels
mA
pF
V
OH
V
OL
I
OH
I
OL
SYM
V
V
CC
= 4.5V/3.0V
V
CC
= 4.5V/3.0V
-
-
45
mA
%
Tested load condition noted for typical values.
T
R
, T
F
CB3LV
Start Up Time
Enable Function
Enable Input Voltage
Disable Input Voltage
Enable Time
Standby Current
Period Jitter, Pk-Pk
Period Jitter, RMS
T
S
V
IH
V
IL
T
PLZ
I
ST
-
-
1.5MHz to 20MHz
20.001MHz to 80MHz
80.001MHz to 200MHz
1.5MHz to 20MHz
20.001MHz to 80MHz
80.001MHz to 200MHz
Application of V
CC
Pin 1 Logic '1', Output Enabled
Pin 1 Logic '0', Output Disabled
Pin 1 Logic '1'
Pin 1 Logic '0', Output Disabled
-
-
C
L
=50pF
C
L
=50pF
C
L
=15pF
C
L
=15pF
C
L
=15pF
C
L
=15pF
-
-
-
-
-
-
-
2.0
-
-
-
-
-
8
5
2.5
6
3
1.5
-
-
-
-
-
-
-
10
8
5
8
5
3
10
-
0.8
200
10
50
5
1
ns
ms
V
ns
µA
ps
Bandwidth 12kHz - 20MHz
Phase Jitter, RMS
-
-
-
Notes:
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
Document No. 008-0256-0
Page 2 - 3
Rev. G
Model CB3 & CB3LV
7.0mm x 5.0mm Low Cost
HCMOS/TTL Clock Oscillator
ELECTRICAL CHARACTERISTICS
LVCMOS OUTPUT WAVEFORM
TEST CIRCUIT, CMOS LOAD
ENABLE TRUTH TABLE
PIN 1
Logic ‘1’
Open
Logic ‘0’
PIN 3
Output
Output
High Imp.
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
1
2
3
4
EOH
GND
Output
V
CC
DESCRIPTION
Enable
Circuit & Package Ground
RF Output
Supply Voltage
MECHANICAL SPECIFICATIONS
PACKAGE DRAWING
MARKING INFORMATION
1. ** – Manufacturing Site Code.
2. XXXMXXXXXX – Frequency is marked with only
leading significant digits before the ‘M’ and
4 – 6 digits after the ‘M’ (including zeros).
Ex. XMXXXXXX [3M579545]
XXMXXXXX [14M31818]
XXXMXXXX [125M0000]
[Note a dash may follow the site code and is acceptable.]
CTS**CB3
XXXMXXXXXX
●
YYWWSTV
3. YYWW – Date code, YY – year, WW – week.
4. ST – Frequency stability/temperature code.
5. V – Voltage code. 3 = 3.3V, 5 = 5.0V.
NOTES
1. Termination pads [e4]. Barrier-plating is nickel
[Ni] with gold [Au] flash plate.
2. Reflow conditions per JEDEC J-STD-020, 260°C
maximum.
3. Moisture Sensitivity Level 1 per JEDEC J-STD-020.
[Refer to Ordering Information.]
SUGGESTED SOLDER PAD GEOMETRY
C
BYPASS
should be
≥
0.01 uF.
Document No. 008-0256-0
Page 3 - 3
Rev. G
FPGA/CPLD
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