74LVC1G32-Q100
Single 2-input OR gate
Rev. 1 — 7 August 2012
Product data sheet
1. General description
The 74LVC1G32-Q100 provides one 2-input OR function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
NXP Semiconductors
74LVC1G32-Q100
Single 2-input OR gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC1G32GW-Q100
74LVC1G32GV-Q100
40 C
to +125
C
40 C
to +125
C
Name
TSSOP5
SC-74A
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
plastic surface-mounted package; 5 leads
Version
SOT353-1
SOT753
Type number
4. Marking
Table 2.
Marking
Marking code
[1]
VG
V32
Type number
74LVC1G32GW-Q100
74LVC1G32GV-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
B
A
Y
4
1
2
A
mna164
mna165
mna166
≥1
4
Y
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
/9&*4
%
$
*1'
DDD
9
&&
<
Fig 4.
Pin configuration SOT353-1 and SOT753
74LVC1G32_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
2 of 13
NXP Semiconductors
74LVC1G32-Q100
Single 2-input OR gate
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
V
CC
Pin description
Pin
1
2
3
4
5
Description
data input
data input
ground (0 V)
data output
supply voltage
7. Functional description
Table 4.
Input
A
L
L
H
H
[1]
Function table
[1]
Output
B
L
H
L
H
Y
L
H
H
H
H = HIGH voltage level; L = LOW voltage level
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP5 and SC-74A packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
74LVC1G32_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
3 of 13
NXP Semiconductors
74LVC1G32-Q100
Single 2-input OR gate
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
V
CC
= 0 V; Power-down mode
Conditions
Min
1.65
0
0
0
40
-
-
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
100 A;
V
CC
= 1.65 V to 5.5 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
24
mA; V
CC
= 3.0 V
I
O
=
32
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
40 C
to +85
C
Min
0.65
V
C
C
40 C
to +125
C
Min
0.65
V
C
C
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.35
V
CC
0.7
0.8
0.3
V
CC
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
Max
-
-
-
-
0.7
0.8
0.3
V
CC
-
-
-
-
-
-
0.10
0.70
0.45
0.60
0.80
0.80
1.7
2.0
0.7
V
CC
-
-
-
-
V
CC
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
1.7
2.0
0.7
V
CC
-
-
-
-
V
CC
0.1
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
0.35
V
CC
V
74LVC1G32_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
4 of 13
NXP Semiconductors
74LVC1G32-Q100
Single 2-input OR gate
Table 7.
Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
I
I
OFF
input leakage
current
power-off
leakage
current
Conditions
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
CC
= 0 V; V
I
or V
O
= 5.5 V
-
-
40 C
to +85
C
Min
Typ
[1]
0.1
0.1
Max
5
10
40 C
to +125
C
Min
-
-
Max
100
200
A
A
Unit
I
CC
I
CC
C
I
supply current V
I
= 5.5 V or GND; I
O
= 0 A;
V
CC
= 1.65 V to 5.5 V
additional
per pin; V
CC
= 2.3 V to 5.5 V;
supply current V
I
= V
CC
0.6 V; I
O
= 0 A
input
capacitance
V
CC
= 3.3 V; V
I
= GND to V
CC
-
-
-
0.1
5
5
10
500
-
-
-
-
200
5000
-
A
A
pF
[1]
All typical values are measured at V
CC
= 3.3 V and T
amb
= 25
C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see
Figure 6.
Symbol
t
pd
Parameter
propagation delay
Conditions
A, B to Y; see
Figure 5
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
C
PD
power dissipation
capacitance
V
I
= GND to V
CC
; V
CC
= 3.3 V
[3]
[2]
40 C
to +85
C
Min
1.0
0.5
0.5
0.5
0.5
-
Typ
[1]
3.1
2.1
2.5
2.1
1.7
16
Max
8.0
5.5
5.5
4.5
4.0
-
40 C
to +125
C
Unit
Min
1.0
0.5
0.5
0.5
0.5
-
Max
10.5
7.0
7.0
6.0
5.5
-
ns
ns
ns
ns
ns
pF
[1]
[2]
[3]
Typical values are measured at T
amb
= 25
C
and V
CC
= 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
t
pd
is the same as t
PLH
and t
PHL
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= (C
PD
V
CC2
f
i
N) + (C
L
V
CC2
f
o
) where:
V
CC
= supply voltage in V,
f
i
= input frequency in MHz,
N = number of inputs switching,
C
L
= output load capacitance in pF,
f
o
= output frequency in MHz.
74LVC1G32_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
5 of 13
Analogue and Mixed Signal
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