DISCRETE SEMICONDUCTORS
DATA SHEET
BSP225
P-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
FEATURES
•
Low R
DS(on)
•
Direct interface to C-MOS, TTL,
etc.
•
High-speed switching
•
No secondary breakdown.
DESCRIPTION
P-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope,
intended for use in relay, high-speed
and line transformer drivers.
PINNING - SOT223
PIN
1
2
3
4
gate
drain
source
drain
1
Top view
2
3
MAM121
BSP225
QUICK REFERENCE DATA
SYMBOL
−V
DS
−I
D
R
DS(on)
−V
GS(th)
PARAMETER
drain-source voltage
drain current
drain-source on-resistance
gate-source threshold voltage
DC value
−I
D
= 200 mA
−V
GS
= 10 V
−I
D
= 1 mA
V
GS
= V
DS
CONDITIONS
MAX.
250
225
15
2.8
UNIT
V
mA
Ω
V
PIN CONFIGURATION
handbook, halfpage
4
d
DESCRIPTION
g
s
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
SYMBOL
−V
DS
±V
GSO
−I
D
−I
DM
P
tot
T
stg
T
j
Note
PARAMETER
drain-source voltage
gate-source voltage
drain current
drain current
total power dissipation
storage temperature range
junction temperature
open drain
DC value
peak value
up to T
amb
= 25
°C
(note 1)
CONDITIONS
MIN.
−
−
−
−
−
−65
−
BSP225
MAX.
250
20
225
600
1.5
150
150
UNIT
V
V
mA
mA
W
°C
°C
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain lead minimum 6 cm
2
.
THERMAL RESISTANCE
SYMBOL
R
th j-a
Note
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain lead minimum 6 cm
2
.
from junction to ambient (note 1)
PARAMETER
VALUE
83.3
UNIT
K/W
April 1995
3
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
−V
(BR)DSS
−I
DSS
±I
GSS
−V
GS(th)
R
DS(on)
Y
fs
C
iss
PARAMETER
drain-source breakdown voltage
drain-source leakage current
gate-source leakage current
gate-source threshold voltage
drain-source on-resistance
transfer admittance
input capacitance
CONDITIONS
−I
D
= 10
µA
V
GS
= 0
−V
DS
= 200 V
V
GS
= 0
V
DS
= 0
±V
GS
= 20 V
−I
D
= 1 mA
V
GS
= V
DS
−I
D
= 200 mA
−V
GS
= 10 V
−I
D
= 200 mA
−V
DS
= 25 V
−V
DS
= 25 V
−V
GS
= 0
f = 1 MHz
−V
DS
= 25 V
−V
GS
= 0
f = 1 MHz
−V
DS
= 25 V
−V
GS
= 0
f = 1 MHz
−I
D
= 250 mA
−V
DD
= 50 V
−V
GS
= 0 to 10 V
−I
D
= 250 mA
−V
DD
= 50 V
−V
GS
= 0 to 10 V
MIN.
250
−
−
0.8
−
100
−
TYP.
−
−
−
−
10
200
65
BSP225
MAX. UNIT
−
1
100
2.8
15
−
90
V
µA
nA
V
Ω
mS
pF
C
oss
output capacitance
−
20
30
pF
C
rss
feedback capacitance
−
6
15
pF
Switching times (see Figs
2
and
3)
t
on
turn-on time
−
5
10
ns
t
off
turn-off time
−
20
30
ns
April 1995
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BSP225
handbook, halfpage
VDD =
−50
V
handbook, halfpage
10 %
INPUT
90 %
0V
−10
V
ID
50
Ω
MBB689
10 %
OUTPUT
90 %
ton
toff
MBB690
Fig.2 Switching time test circuit.
Fig.3 Input and output waveforms.
handbook,
2
MBB693
Ptot
(W)
1.6
handbook, halfpage
−1
MDA706
ID
VGS =
−10
V
−6
V
(A)
−0.8
1.2
−0.6
−5
V
0.8
−0.4
−4
V
0.4
−0.2
−3
V
0
0
50
100
150
200
Tamb (°C)
0
0
−5
−10
−15
−20
−25
VDS (V)
Fig.4 Power derating curve.
Fig.5 Typical output characteristics; T
j
= 25
°C.
April 1995
5
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