BUK9875-100A
19 March 2014
SO
T2
23
N-channel TrenchMOS logic level FET
Product data sheet
1. General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
2. Features and benefits
•
•
•
Low conduction losses due to low on-state resistance
Q101 compliant
Suitable for logic level gate drive sources
3. Applications
•
•
•
12 V, 24 V and 42 V loads
Automotive and general purpose power switching
Motors, lamps and solenoids
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 150 °C
V
GS
= 5 V; T
sp
= 25 °C;
Fig. 2; Fig. 3
T
sp
= 25 °C;
Fig. 1
V
GS
= 4.5 V; I
D
= 8 A; T
j
= 25 °C
V
GS
= 10 V; I
D
= 8 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 8 A; T
j
= 25 °C;
Fig. 12;
Fig. 13
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-
source avalanche
energy
I
D
= 7 A; V
sup
≤ 100 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
-
-
49
mJ
Min
-
-
-
Typ
-
-
-
Max
100
7
8
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
-
-
-
-
62
64
84
72
75
mΩ
mΩ
mΩ
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NXP Semiconductors
BUK9875-100A
N-channel TrenchMOS logic level FET
5. Pinning information
Table 2.
Pin
1
2
3
4
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
drain
G
Simplified outline
4
Graphic symbol
D
1
2
3
SC-73 (SOT223)
mbb076
S
6. Ordering information
Table 3.
Ordering information
Package
Name
BUK9875-100A
BUK9875-100A/CU
SC-73
SC-73
Description
plastic surface-mounted package with increased heatsink; 4
leads
plastic surface-mounted package with increased heatsink; 4
leads
Version
SOT223
SOT223
Type number
7. Marking
Table 4.
Marking codes
Marking code
987510A
987510
Type number
BUK9875-100A
BUK9875-100A/CU
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
P
tot
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
T
sp
= 25 °C;
Fig. 1
T
sp
= 25 °C; V
GS
= 5 V;
Fig. 2; Fig. 3
T
sp
= 100 °C; V
GS
= 5 V;
Fig. 2
I
DM
BUK9875-100A
Conditions
T
j
≥ 25 °C; T
j
≤ 150 °C
R
GS
= 20 kΩ
Min
-
-
-10
-
-
-
-
Max
100
100
10
8
7
4
28
Unit
V
V
V
W
A
A
A
peak drain current
T
sp
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 3
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
19 March 2014
2 / 12
NXP Semiconductors
BUK9875-100A
N-channel TrenchMOS logic level FET
Symbol
T
stg
T
j
V
GSM
I
S
I
SM
E
DS(AL)S
Parameter
storage temperature
junction temperature
peak gate-source voltage
Conditions
Min
-55
-55
Max
150
150
15
Unit
°C
°C
V
pulsed; t
p
≤ 50 µs
T
sp
= 25 °C
pulsed; t
p
≤ 10 µs; T
sp
= 25 °C
I
D
= 7 A; V
sup
≤ 100 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
03aa17
-15
Source-drain diode
source current
peak source current
-
-
7
28
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
-
49
mJ
120
P
der
(%)
80
120
I
der
(%)
80
03aa25
40
40
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of solder point temperature
Fig. 2.
Normalized continuous drain current as a
function of solder point temperature
BUK9875-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
19 March 2014
3 / 12
NXP Semiconductors
BUK9875-100A
N-channel TrenchMOS logic level FET
10
2
I
D
(A)
10
R
DSon
= V
DS
/ I
D
t
p
= 10 µs
100 µs
1 ms
1
P
10
- 1
t
p
10
- 2
10
- 1
t
T
1
10
10
2
V
DS
(V)
δ=
t
p
T
D.C.
10 ms
100 ms
03nc17
10
3
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
10
2
Z
th(j-sp)
(K/W)
10
δ = 0.5
0.2
1
0.1
0.05
0.02
10
- 1
Single Shot
10
- 2
10
- 6
10
- 5
10
- 4
10
- 3
10
- 2
10
- 1
1
t
p
P
δ=
t
p
T
Conditions
Min
-
Typ
-
Max
15
Unit
K/W
R
th(j-a)
Fig. 4
-
120
-
K/W
03nc16
t
T
10
t
p
(s)
10
2
Fig. 4.
Transient thermal impedance from junction to solder point as a function of pulse duration
BUK9875-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
19 March 2014
4 / 12
NXP Semiconductors
BUK9875-100A
N-channel TrenchMOS logic level FET
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C;
Fig. 11
I
DSS
drain leakage current
V
DS
= 100 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 100 V; V
GS
= 0 V; T
j
= 150 °C
I
GSS
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 8 A; T
j
= 150 °C;
Fig. 12; Fig. 13
V
GS
= 4.5 V; I
D
= 8 A; T
j
= 25 °C
V
GS
= 10 V; I
D
= 8 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 8 A; T
j
= 25 °C;
Fig. 12;
Fig. 13
Dynamic characteristics
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
V
DS
= 30 V; R
L
= 1.2 Ω; V
GS
= 5 V;
R
G(ext)
= 10 Ω; T
j
= 25 °C
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
T
j
= 25 °C;
Fig. 14
-
-
-
-
-
-
-
1270
140
90
13
120
58
57
1690
167
124
-
-
-
-
pF
pF
pF
ns
ns
ns
ns
-
-
-
-
62
64
84
72
75
mΩ
mΩ
mΩ
-
-
-
-
-
0.05
-
2
2
-
10
500
100
100
162
µA
µA
nA
nA
mΩ
0.6
-
-
V
-
-
2.3
V
Min
100
89
1
Typ
-
-
1.5
Max
-
-
2
Unit
V
V
V
Static characteristics
V
GS(th)
Source-drain diode
source-drain voltage
reverse recovery time
recovered charge
I
S
= 5 A; V
GS
= 0 V; T
j
= 25 °C;
Fig. 15
I
S
= 20 A; dI
S
/dt = -100 A/µs;
V
GS
= -10 V; V
DS
= 30 V; T
j
= 25 °C
-
-
-
0.85
63
220
1.2
-
-
V
ns
nC
BUK9875-100A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
19 March 2014
5 / 12
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