K3N5V1000E-DC100 datasheet, PDF

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K3N5V1000E-DC100: DescriptionMASK ROM, 1MX16, 100ns, CMOS, PDIP42, 0.600 INCH, DIP-42; Categorystorage storage; File Size52KB，3 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K3N5V1000E-DC100 Overview

MASK ROM, 1MX16, 100ns, CMOS, PDIP42, 0.600 INCH, DIP-42

K3N5V1000E-DC100 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	DIP
package instruction	DIP,
Contacts	42
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	100 ns
Spare memory width	8
JESD-30 code	R-PDIP-T42
length	52.42 mm
memory density	16777216 bit
Memory IC Type	MASK ROM
memory width	16
Number of functions	1
Number of terminals	42
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX16
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

K3N5V1000E-DC100 Preview

K3N5V(U)1000E-D(G)C

16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM

FEATURES

•

Switchable organization

2,097,152 x 8(byte mode)

1,048,576 x 16(word mode)

•

Fast access time

3.3V Operation : 100ns(Max.)@C

=50pF,

120ns(Max.)@C

=100pF

3.0V Operation : 120ns(Max.)@C

=100pF

•

Supply voltage : single +3.0V/single +3.3V

•

Current consumption

Operating : 40mA(Max.)

Standby : 30µA(Max.)

•

Fully static operation

•

All inputs and outputs TTL compatible

•

Three state outputs

•

Package

-. K3N5V(U)1000E-DC : 42-DIP-600

-. K3N5V(U)1000E-GC : 44-SOP-600

CMOS MASK ROM

GENERAL DESCRIPTION

The K3N5V(U)1000E-D(G)C is a fully static mask programma-

ble ROM fabricated using silicon gate CMOS process technol-

ogy, and is organized either as 2,097,152 x 8 bit(byte mode) or

as 1,048,576x16 bit(word mode) depending on BHE voltage

level.(See mode selection table)

This device operates with 3.0V or 3.3V power supply, and all

inputs and outputs are TTL compatible.

Because of its asynchronous operation, it requires no external

clock assuring extremely easy operation.

It is suitable for use in program memory of microprocessor, and

data memory, character generator.

The K3N5V(U)1000E-DC is packaged in a 42-DIP and the

K3N5V(U)1000E-GC in a 44-SOP.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

-1

BUFFERS

AND

DECODER

MEMORY CELL

MATRIX

(1,048,576x16/

2,097,152x8)

42 A

41 A

40 A

39 A

38 A

37 A

36 A

35 A

34 A

33 A

32 BHE

N.C 1

44 N.C

43 A

42 A

41 A

40 A

39 A

38 A

37 A

36 A

35 A

34 A

33 BHE

32 V

31 Q

-1

30 Q

29 Q

28 Q

27 Q

26 Q

25 Q

24 Q

23 V

BUFFERS

AND

DECODER

SENSE AMP.

DATA OUT

BUFFERS

. . .

CE 11

OE 13

DIP

BHE

CONTROL

LOGIC

Pin Name

- A

- Q

-1

BHE

N.C

Pin Function

Address Inputs

Data Outputs

Output 15(Word mode)/

LSB Address(Byte mode)

Word/Byte selection

Chip Enable

Output Enable

Power

Ground

No Connection

31 V

CE 12

30 Q

-1

29 Q

OE 14

28 Q

27 Q

26 Q

25 Q

24 Q

23 Q

22 V

SOP

K3N5V(U)1000E-DC

K3N5V(U)1000E-GC

K3N5V(U)1000E-D(G)C

ABSOLUTE MAXIMUM RATINGS

Item

Voltage on Any Pin Relative to V

Temperature Under Bias

Storage Temperature

Symbol

BIAS

STG

Rating

CMOS MASK ROM

Unit

°C

-0.3 to +4.5

-10 to +85

-55 to +150

NOTE

: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the

conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to V

, T

=0 to 70°C)

Item

Supply Voltage

Symbol

Min

2.7/3.0

Typ

3.0/3.3

Max

3.3/3.6

Unit

DC CHARACTERISTICS

Parameter

Operating Current

Standby Current(TTL)

Standby Current(CMOS)

Input Leakage Current

Output Leakage Current

Input High Voltage, All Inputs

Input Low Voltage, All Inputs

Output High Voltage Level

Output Low Voltage Level

Symbol

SB1

SB2

= -400µA

= 2.1mA

Test Conditions

Cycle=5MHz, all outputs open, CE=OE=V

=0.45V to 2.4V (AC Test Condition)

CE=V

, all outputs open

CE=V

, all outputs open

=0 to V

OUT

=0 to V

Vcc=3.3V±0.3V

Vcc=3.0V

0.3V

2.0

-0.3

2.4

Min

Max

500

+0.3

0.6

0.4

µA

Unit

NOTE

: Minimum DC Voltage(V

) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.

Maximum DC voltage on input pins(V

) is V

+0.3V which, during transitions, may overshoot to V

+2.0V for periods <20ns.

MODE SELECTION

BHE

-1

Output

Input

Mode

Standby

Operating

Data

High-Z

: Dout

: Hi-Z

Power

Standby

Active

CAPACITANCE

=25°C, f=1.0MHz)

Item

Output Capacitance

Input Capacitance

Symbol

OUT

Test Conditions

OUT

=0V

Min

Max

Unit

NOTE

: Capacitance is periodically sampled and not 100% tested.

K3N5V(U)1000E-D(G)C

CMOS MASK ROM

AC CHARACTERISTICS

=0°C to +70°C, V

=3.3V/3.0V±0.3V, unless otherwise noted.)

TEST CONDITIONS

Item

Input Pulse Levels

Input Rise and Fall Times

Input and Output timing Levels

Output Loads

Value

0.45V to 2.4V

10ns

1.5V

1 TTL Gate and C

=50pF or 100pF

READ CYCLE

Item

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

Output or Chip Disable to

Output High-Z

Output Hold from Address Change

Symbol

ACE

K3N5V1000E-D(G)C10

=50pF)

Min

100

Max

K3N5V1000E-D(G)C12 K3N5U1000E-D(G)C12

=100pF)

Min

120

Max

Min

120

Max

Unit

TIMING DIAGRAM

READ

ADD

-1(*1)

ACE

ADD1

ADD2

DF(*3)

OUT

15(*2)

VALID DATA

NOTES :

*1. Byte Mode only. A

-1

is Least Significant Bit Address.(BHE = V

)

*2. Word Mode only.(BHE = V

)

*3. t

is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V

or V

level.

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