A3PN125 datasheet, PDF - EEWORLD Datasheet

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A3PN125: DescriptionFPGA, 1536 CLBS, 60000 GATES, PQFP100; Categorysemiconductor Programmable logic devices; File Size6MB，114 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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A3PN125 Overview

FPGA, 1536 CLBS, 60000 GATES, PQFP100

A3PN125 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	14 × 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	MATTE Tin
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
organize	1536 CLBS, 60,000 doors
Number of configurable logic modules	1536
Programmable logic type	FIELD PROGRAMMABLE GATE array
Number of equivalent gate circuits	60000

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Revision 11

ProASIC3 nano Flash FPGAs

Features and Benefits

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Advanced I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

†

• FlashLock

Designed to Secure FPGA Contents

Clock Conditioning Circuit (CCC) and PLL

†

Low Power

•

Low Power

nano Products

1.5 V Core Voltage for Low Power

Support for 1.5 V-Only Systems

Low-Impedance Flash Switches

ProASIC

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18 organization)

†

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Enhanced Commercial Temperature Range

• –20°C to +70°C

Table 1 • ProASIC3 nano Devices

ProASIC3 nano Devices

ProASIC3 nano-Z Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

A3PN010

10,000

260

–

A3PN015

A3PN020

15,000

128

384

–

QN68

20,000

172

520

–

QN68

30,000

256

768

–

QN48, QN68

VQ100

A3PN060

60,000

512

1,536

Yes

A3PN125

125,000

1,024

3,072

Yes

A3PN250

A3N250Z

250,000

2,048

6,144

Yes

A3PN030Z

1,2

A3PN060Z

A3PN125Z

FlashROM Kbits

Secure (AES) ISP

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

Package Pins

QFN

VQFP

–

QN48

Integrated PLL in CCCs

VQ100

Notes:

1. Not recommended for new designs.

2. A3PN030Z and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the

ProASIC3

and

ProASIC3E

datasheets.

† A3PN030 and smaller devices do not support this feature.

January 2013

ProASIC3 nano Flash FPGAs

Table of Contents

ProASIC3 nano Device Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3 nano DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-3

3-4

Package Pin Assignments

48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

R ev i si o n 1 1

A3PN125 Related Products

	A3PN125	A3PN010	A3PN020	A3PN250
Description	FPGA, 1536 CLBS, 60000 GATES, PQFP100	FPGA, 1536 CLBS, 60000 GATES, PQFP100	FPGA, 1536 CLBS, 60000 GATES, PQFP100	FPGA, 1536 CLBS, 60000 GATES, PQFP100
Number of functions	1	1	1	1
Number of terminals	100	100	100	100
Maximum operating temperature	85 Cel	85 Cel	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel	-40 Cel	-40 Cel
Maximum supply/operating voltage	1.58 V	1.58 V	1.58 V	1.58 V
Minimum supply/operating voltage	1.42 V	1.42 V	1.42 V	1.42 V
Rated supply voltage	1.5 V	1.5 V	1.5 V	1.5 V
Processing package description	14 × 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100	14 × 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100	14 × 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100	14 × 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
state	ACTIVE	ACTIVE	ACTIVE	ACTIVE
Craftsmanship	CMOS	CMOS	CMOS	CMOS
packaging shape	SQUARE	SQUARE	SQUARE	SQUARE
Package Size	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH	FLATPACK, THIN PROFILE, FINE PITCH
surface mount	Yes	Yes	Yes	Yes
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal spacing	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm
terminal coating	MATTE Tin	MATTE Tin	MATTE Tin	MATTE Tin
Terminal location	Four	Four	Four	Four
Packaging Materials	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
organize	1536 CLBS, 60,000 doors	1536 CLBS, 60,000 doors	1536 CLBS, 60,000 doors	1536 CLBS, 60,000 doors
Number of configurable logic modules	1536	1536	1536	1536
Programmable logic type	FIELD PROGRAMMABLE GATE array	FIELD PROGRAMMABLE GATE array	FIELD PROGRAMMABLE GATE array	FIELD PROGRAMMABLE GATE array
Number of equivalent gate circuits	60000	60000	60000	60000

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