DD-03182 SERIES
ARINC 429 LINE DRIVER
DESCRIPTION
The DD-03182 device is a line driver
chip that transmits data on the serial
data bus in accordance with the
“ARINC Specification 429 Mark 33
Digital Information Transfer System”
(ARINC 429). This device can be used
with DDC’s DD-03296 discrete-to-digi-
tal device, in conjunction with the DD-
03282 transceiver chip or the DD-
00429 microprocessor interface.
The line driver receives TTL informa-
tion on the Data
A
/Data
B
input pins
and transmits it out on the A
OUT
/B
OUT
output pins. The output voltage level
is programmable via the V
REF
input
pin. The output pins are also protect-
ed against short circuits from aircraft
power. The slew rate of the DD-03182
can be programmed for either High
(100 kbit) or Low (12.5 kbit) speed via
two external timing capacitors con-
nected to the C
A
/C
B
input pins.
FEATURES
•
Plastic 14-Pin SOIC Package
Available with or without Fuse
•
Pin-For-Pin Alternative for Most
Harris/Holt/Raytheon Applications
APPLICATIONS
The DD-03182 can be used for many
different applications ranging from
flight critical to nonessential. Surface
mount, DIP and PLCC package con-
figurations are available. Military tem-
perature range is also available if
required.
•
Programmable Output Voltage Level
•
Short-Circuit Protection on Outputs
•
Programmable Slew and Data Rates
+V C
A
DATA (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
OUTPUT
DRIVER (A)
R
OUT
2
A
OUT
CLOCK
V
REF
SYNC
DATA (B)
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
GND
OVERVOLTAGE
PROTECTION
(OPTIONAL)
OUTPUT
DRIVER (B)
R
OUT
2
B
OUT
V
1
CURRENT
REGULATOR
BIAS
-V
C
B
Overvoltage Protection optional for
DD-03182VP only.
FIGURE 1. DD-03182 BLOCK DIAGRAM
©
1993, 1999 Data Device Corporation
TABLE 1. DD-03182 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM
RATINGS
VOLTAGE BETWEEN
PINS
+V and -V
V
1
and GND
V
REF
and GND
Output Short-circuit
Protection
Output Overvoltage
Protection
Power Dissipation
POWER SUPPLY
REQUIREMENTS
+V
-V
V
1
V
REF
(for ARINC 429)
V
REF
(for other applica-
tions)
THERMAL
Operating Ambient
Temperature
Ceramic
Plastic
Storage Temperature
Lead Temperature
(localized 10 sec
duration)
Thermal Resistance:
Junction to Case
θ
jc
DD-03182DC
Junction to Ambient
θ
ja
(see Note 3)
DD-03182DC
DD-03182PP
DD-03182GP
DD-03182VP
Max. Junction Temperature
SIZE
DD-03182VP
DD-03182DC
DD-03182GP
DD-03182PP
WEIGHT
DD-03182VP
DD-03182DC
DD-03182GP
DD-03182PP
UNITS
MIN
TYP
MAX
GENERAL
The ARINC 429 standard is widely used in the civil aerospace
market (commercial aircraft). ARINC 429 operates at either 12
to 14.5 or 100 kbits on a simplex bus. A simplex bus is one on
which there is only one transmitter but multiple receivers (up to a
maximum of 20 in the case of 429). If receipt of a message by a
given sink R(n) is required by the source T, a separate bus with
R(n) as the source and T as the sink is required. To those
designers who focus on military systems, a simplex bus may
seem cumbersome, but it can be readily certified for civil aircraft.
Communications on 429 buses use 32-bit words with odd parity.
The waveform is a bipolar return to zero with each bit lasting
either 70 or 83µs ±2.5 percent, or 10µs, ±2.5 percent, depend-
ing on whether the bus is low- or high-speed. A low-speed bus
is used for general purpose, low critical applications. A high-
speed bus is used for transmitting large quantities of data or
flight critical information.
ARINC 429 imposes relatively modest and readily achievable
performance demands on the hardware. FIGURE 2 is a general
schematic of a 429 bus. The transmitter output impedance
should be in the range of 75 to 85
Ω,
equally divided between the
two leads. The output voltage, V
o
, is 10 V and is generated by
imposing equal but opposite polarity voltages on the two leads.
The null voltage is 0.5 V. For the receiver, the input resistance
shall be greater than 12,000
Ω
and the input differential capaci-
tance and the capacitance to ground shall, in both cases, be less
than 50 pF. The 12,000
Ω
minimum input resistance ensures
that up to 20 receivers can be on the bus without overloading it
and minimizes receiver interaction under fault conditions. To pre-
clude continued receiver operation in a lead-to-ground fault con-
dition, 429 has established the range of acceptable receiver volt-
age levels to be +6.5 to +13.0 V and -6.5 to -13.0 V and null lev-
els from +2.5 to -2.5 V. Any signals falling outside of these lev-
els will be ignored. Also note that a lead-to-ground fault will pro-
duce a differential voltage swing up 5.5 V. FIGURE 4 shows the
waveforms required by 429 and permissible levels for transmitter
and receiver voltages.
V
V
V
See Note 1
See Note 2
See TABLE 2
40
7
6
VDC
VDC
VDC
VDC
VDC
11.4
-11.4
4.75
4.75
0
15
-15
5
5
16.5
-16.5
5.25
5.25
°C
°C
°C
°C
-55
-40
-65
+125
+85
+150
+300
°C/W
15
°C/W
°C/W
°C/W
°C/W
°C
in.
(mm.)
in.
(mm.)
in.
(mm.)
in.
(mm.)
oz. (g.)
oz. (g.)
oz. (g.)
oz. (g.)
75
95
115
130
175
0.344 x 0.158 x 0.069
(8.737 x 4.013 x 1.753)
0.785 x 0.291 x 0.160
(19.939 x 7.391 x 4.064)
0.413 x 0.300 x 0.082
(10.490 x 7.620 x2.080)
0.454 x 0.454 x 0.155
(11.53 x 11.53 x 3.94)
0.01
0.08
0.02
0.04
(0.28)
(2.26)
(0.57)
(1.13)
Signal Leads
A
B
A
B
Transmitter
Shield
Receiver
Notes:
1. Both outputs can be shorted to ground or to each other, at +25°C ambient tem-
perature.
2. Both outputs are fused between 0.5 Amp DC and 1.0 Amp DC to prevent an
overvoltage fault from coupling onto the system power bus.
3. Thermal resistance when mounted on a 4" x 4" FR4 PC board in a horizontal
position, still air.
To Other Receivers
(max. total of 20)
FIGURE 2. GENERALIZED 429 BUS
2
TABLE 2. DD-03182 POWER DISSIPATION FOR CONTINUOUS ARINC 429 TRANSMISSION
V
REF
and
DATA RATE (KBPS)
+V @
-V @
LOAD POWER
LOAD
V
1
@
15 V
-15 V
(mW)
(Note 2)
(mA)
(mA)
(Note 1)
5V
R
C
(Note 3)
(Note 3)
(mA)
(Ω)
(pF)
0 TO 100
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
100
100
100
100
100
100
100
100
100
Notes:
CHIP POWER
(mW)
(Note 1)
No load
2000
2000
2000
800
800
800
400
400
400
2000
2000
2000
800
800
800
400
400
400
0
1000
10,000
30,000
1000
10,000
30,000
1000
10,000
30,000
1000
3,000
10,000
1000
3,000
10,000
1000
3,000
10,000
2.5
4.6
6.5
11.3
7.8
8.9
13.5
12.5
13
16.2
5.8
9.3
22.2
8.4
11.4
23.1
12.8
14.3
24.4
-5.0
-7.1
-8.9
-13.8
-10.3
-11.4
-16
-15.1
-15.5
-18.7
-8.3
-11.7
-24.7
-11
-14
-25.7
-15.3
-16.8
-26.9
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
0
19
19
19
42
42
42
71
71
71
19
19
19
42
42
42
71
71
71
120
158
206
336
219
249
371
317
329
414
189
281
627
237
317
629
324
364
633
1. Supply current data is at 100% duty cycle. Load and chip power is calculated as 89% duty cycle (32 bits,/36 bits).
2. Data is not presented for 30,000 pF at 100 kbps. This is considered an unrealistic load for high-speed operation.
3. For 12 volt power supplies, multiply tabulated values of chip power by 0.8.
TABLE 3. DD-03182 DC ELECTRICAL CHARACTERISTICS
CONDITIONS:
Ambient Temperature is in accordance with the temperature range of device type ordered;
+V = +15 VDC ±10%; -V = -15 VDC ±10%; V
1
= V
REF
= +5 VDC ±5%
*.
PARAMETER (SYMBOL)
Quiescent +V Supply Current (IQ+V)
Quiescent -V Supply Current (IQ-V)
Quiescent V1 Supply Current (IQV1)
Quiescent VREF supply current (IQVREF)
Logic 1 input V (VIH)
Logic 1 input I (IIH)
Logic 0 input V (VIL)
Logic 0 input I (IIL)
Output voltage high: +1 (VOH)
Output voltage null: 0 (VNULL)
Output voltage low: -1 (VOL)
Timing capacitor charge current:
CA [+1] CB [-1] (ICT+)
CA [-1] CB [+1] (ICT-)
+V Short-circuit supply current (ISC [+V])
-V Short-circuit supply current (ISC [-V])
Output resistance each output (ROUT/2)
is at +25°C only.
Input capacitance (CIN)
UNITS
mA
mA
mA
µA
V
µA
V
µA
V
mV
V
V
REF
-250 mV
-250
-V
REF
-250 mV
-V
REF
V
REF
2.0
10
0.6
-20
V
REF
+250 mV
+250
-V
REF
+250 mV
MIN
TYP
2.5
5
4.4
10
MAX
TEST CONDITIONS
No load 429 mode.
DATA = CLOCK = SYNC = L
No load 429 mode.
DATA = CLOCK = SYNC = L
No load 429 mode.
DATA = CLOCK = SYNC = L
No load 429 mode.
DATA = CLOCK = SYNC = L
No load
No load
No load
No load (Pin 15 I
IL
= -2 mA max.)
No load 429 Mode
No load 429 Mode
No load 429 Mode
No load 429 Mode.
SYNC = CLOCK = H
C
A
and C
B
held at 0
+150
-150
30
37.5
45
15
Output short to GND.
Output short to GND.
µA
µA
mA
mA
ohms
pF
+200
-200
*
Note: The device will operate with +V and -V supplies at ±12 VDC ±5% in accordance with the temperature range of the device type ordered.
3
The DD-03182 line driver is designed to take data from a box and
place it on the data bus. The serial data is presented on DATA(A)
and DATA(B) inputs in a dual rail format. The driver is enabled by
the SYNC and CLOCK inputs. The output voltage level is pro-
grammed by the V
REF
input and is normally tied to +5 VDC along
with V
1
to produce output levels of +5V, 0V, and
-5 V on each output for 10 V differential outputs (see FIGURE 3).
The outputs are fused for fail-safe protection against shorts to
aircraft power. The output slew rate is controlled by external tim-
ing capacitors on C
A
and C
B
. Typical Values are 75 pF for
100 kHz data and 500 pF for 12.5 kHz data.
The cable used in 429 buses is a twisted, shielded pair of 20- to
26-gauge conductors. The shield is grounded at both ends of the
cable run and at all production breaks. Although there is no
specification placed on the cable impedance, it generally falls in
the range of 60 to 80
Ω.
TABLE 4. DD-03182 TRUTH TABLE
SYNC
(Note 1)
L
X
H
H
H
H
CLOCK
(Note 1)
X
L
H
H
H
H
DATA (A)
(Note 1)
X
X
L
H
H
L
DATA (B)
(Note 1)
X
X
L
H
L
H
A
OUT
(Note 2)
0
0
0
0
+1
-1
B
OUT
(Note 2)
0
0
0
0
-1
+1
COMMENTS
Null
Null
Null
Null
Logic 1
Logic 0
Notes:
1. X = Don’t care.
2. The A
OUT
/B
OUT
notation is as follows:
+1 = V
REF
volts
0=0
A
IN
DATA (A)
B
IN
DATA (B)
+V
REF
A
-V
+V
B
-V
OUT
REF
0V
REF
OUT
REF
0V
Note: The output slew rates are controlled by timing capacitors C
A
and C
B
. They are charged to ±200µA (nominal).
Slew rate (SR) is calculated by SR = 200/C (V/µs), where C is in pF.
FIGURE 3. ARINC 429 WAVEFORM
4
SLEW RATE VS. TIMING CAPACITOR VALUES
The output slew rates are controlled by timing capacitors C
A
and
C
B
, and are charged by ±200 µA (nominal). Slew rate (SR) is cal-
culated by:
SR = 200/C (V/µsec), where C is in pF (equation 1).
(0.4 V/µsec)(10) = 4.0 V
SR = 4/(Rise Time)
0.8 µsec = 4V/5 µsec
Capacitor = 200/0.8 = 250 pF
0.267 µsec = 4V/15 µsec Capacitor = 200/0.267 = 750 pF
HIGH-SPEED SLEW RATE
C
A
and C
B
= 75 pF for 100 kbps
From equation 1: 200/75 = 2.67 V/µsec
10% - 90% = 0.5 V to 4.5 V
∆
= 4.0 V
For 100 kbps bit rate, the slew rate specification is 1.5 µsec
±0.5 µsec. Slew rate range (1.0 to 2.0 µsec).
200/SR = Capacitor, in pF
200/2.67 = 75 pF
(2.67 V/µsec)(1.5) = 4.0 V
SR = 4/(Rise Time)
4 µsec = 4V/1 µsec
2 µsec = 4V/2 µsec
Capacitor = 200/4 = 50 pF
Capacitor = 200/2 = 100 pF
DD-03182 PIN FUNCTIONS
Refer to FIGURES 7, 8 and 9 and TABLE 5 for specific package
pin configurations.
V
REF
(Input) – the voltage on V
REF
sets the output voltage levels
on A
OUT
and B
OUT
. The output logic level swings between
+V
REF
volts, 0 volts and -V
REF
volts.
N/C – No Connection
SYNC (Input) – Logic 0 outputs will be forced to NULL or MARK
state. Logic 1 enables data transmission.
CLOCK (Input) – Logic 0 outputs will be forced to NULL or
MARK state. Logic 1 enables data transmission.
DATA(A)/DATA(B) (Inputs) – These signals contain the serial
data to be transmitted on the ARINC 429 data bus.
C
A
/C
B
(Analog) – External timing capacitors are tied from these
points to ground to establish the output signal slew rate.
Typically, C
A
=C
B
=75 pF for 100 kHz data and C
A
=C
B
=500 pF for
12.5 kHz data.
A
OUT
/B
OUT
(Output) – These are the line driver outputs which
are connected to the aircraft serial data bus.
-V (Input) – This is the negative supply input (-15 VDC nominal).
GND – Ground
+V (Input) – This is the positive supply input (+15 VDC nominal).
V
1
(Input) – This is the logic supply input (+5 VDC nominal).
TABLE 5. DD-03182 PINOUTS
LOW-SPEED SLEW RATE
C
A
and C
B
= 500 pF for 12.5 kbps
From equation 1: 200/500 = 0.4 V/µsec
For 12.5 kbps bit rate, the slew rate specification is 10 µsec
±5.0 µsec. Slew rate range (5 to 15 µsec).
200/SR = Capacitor in pF
200/0.4 = 500 pF
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DC OR GP
PACKAGE
V
REF
N/C
SYNC
DATA (A)
C
A
A
OUT
-V
GND
+V
N/C
B
OUT
C
B
DATA (B)
CLOCK
PP PACKAGE VP PACKAGE PIN NUMBER
V
REF
N/C
GND
SYNC
N/C
DATA (A)
N/C
N/C
C
A
N/C
N/C
N/C
A
OUT
-V
V
REF
N/C
SYNC
DATA (A)
C
A
A
OUT
-V
GND
+V
B
OUT
C
B
DATA (B)
CLOCK
V
1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DC OR GP
PACKAGE
N/C
V
1
PP PACKAGE
GND
+V
B
OUT
N/C
N/C
N/C
N/C
C
B
DATA (B)
N/C
CLOCK
N/C
N/C
V
1
5
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