TSX88915TMR70 datasheet, PDF - EEWORLD Datasheet

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TSX88915TMR70: DescriptionPLL Based Clock Driver, 7 True Output(s), 1 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA-29; Categorylogic logic; File Size168KB，20 Pages; Manufacturere2v technologies

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TSX88915TMR70 Overview

PLL Based Clock Driver, 7 True Output(s), 1 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA-29

TSX88915TMR70 Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	PGA
package instruction	PGA,
Contacts	29
Reach Compliance Code	compliant
Input adjustment	MUX
JESD-30 code	S-CPGA-P29
length	15.24 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs	1
Number of terminals	29
Actual output times	7
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.75 ns
Maximum seat height	4.117 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	15.24 mm
minfmax	70 MHz

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TS88915T

LOW SKEW CMOS PLL CLOCK DRIVER

3-State 70 and 100 MHz Versions

DESCRIPTION

The TS88915T Clock Driver utilizes a phazed–locked loop

(PLL) technology to lock its low skew outputs’ frequency and

phase onto an input reference clock. It is designed to provide

clock distribution for high performance microprocessors such

as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge,

RAM’s, MMU’s...

MAIN FEATURES

Vcc = 5V

5 %

MILITARY TEMPERATURE RANGE

TS68040 FULL COMPATIBLE

FIVE LOW SKEW OUTPUTS

Five Outputs (Q0-Q4) with Output–to–Output skew < 500

ps each being phase end frequency locked to the SYNC

input.

ADDITIONAL OUTPUTS

Three additional outputs are available :

– The 2X_Q output runs twice the system ”Q” frequency.

– The Q/2 output runs at 1/2 the system ”Q” frequency.

– The Q5 output is inverted (180° phase shift).

TWO SELECTABLE CLOCK INPUTS

– Two selectable CLOCK inputs are available for test or

redundancy purposes.

– Test Mode pin (PLL_EN) provided for low frequency test-

ing.

– All outputs can go into high impedance (3-state) for board

test purpose.

INPUT FREQUENCY RANGE FROM 5MHz to 2X_Q

FMAX

THREE INPUT/OUTPUT RATIOS

Input/Output phase–locked frequency ratios of 1:2, 1:1 and

2:1 are available.

LOW PART-TO-PART SKEW

The phase variation from part–to–part between the SYNC

and FEEDBACK inputs is less than 550 ps (derived from the

specification, which defines the part-to-part skew).

CMOS AND TTL COMPATIBLE

– All outputs can drive either CMOS or TTL inputs.

– All inputs are TTL-level compatible.

LOCK Indicator (LOCK) indicated a phase–locked

state.

R Suffix

PGA 29

Ceramic Pin grid array

W suffix

LDCC 28

Leaded Ceramic Chip Carrier

SCREENING / QUALITY

This product is manufactured :

based upon the generic flow of MIL–STD–883.

or according to TCS standard.

April 1999

1/20

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