Advance Information
MPC7410EC
Rev. 2, 10/2003
MPC7410 RISC
Microprocessor
Hardware Specifications
The MPC7410 is a PowerPC™ microprocessor. The MPC7410 is a reduced instruction set
computing (RISC) microprocessor that implements the PowerPC instruction set architecture.
This document describes pertinent electrical and physical characteristics of the MPC7410. For
functional characteristics of the processor, refer to the
MPC7410 RISC Microprocessor User’s
Manual
.
This document contains the following topics:
Topic
Section 1.1, “Overview”
Section 1.2, “Features”
Section 1.3, “General Parameters”
Section 1.4, “Electrical and Thermal Characteristics”
Section 1.5, “Pin Assignments”
Section 1.6, “Pinout Listings”
Section 1.7, “Package Description”
Section 1.8, “System Design Information”
Section 1.9, “Document Revision History”
Section 1.10, “Ordering Information”
Page
2
2
7
8
24
25
29
31
44
47
To locate any published errata or updates for this document, refer to the web site at
http://www.motorola.com/semiconductors.
Overview
1.1
Overview
The MPC7410 is the second implementation of the fourth generation (G4) microprocessors from Motorola.
The MPC7410 implements the full PowerPC 32-bit architecture and is targeted at both computing and
embedded systems applications.
Some comments on the MPC7410 with respect to the MPC750:
•
•
•
•
•
•
•
The MPC7410 adds an implementation of the new AltiVec™ technology instruction set.
The MPC7410 includes significant improvements in memory subsystem (MSS) bandwidth and
offers an optional, high-bandwidth MPX bus interface.
The MPC7410 adds full hardware-based multiprocessing capability, including a five-state cache
coherency protocol (four MESI states plus a fifth state for shared intervention).
The MPC7410 is implemented in a next generation process technology for core frequency
improvement.
The MPC7410 floating-point unit has been improved to make latency equal for double- and
single-precision operations involving multiplication.
The completion queue has been extended to eight slots.
There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms,
or the branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch,
execute, complete/writeback).
The MPC7410 adds configurable direct-mapped SRAM capability to the L2 cache interface.
The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements
a 19th L2 address pin (L2ASPARE on the MPC7400) in order to support additional address range.
The MPC7410 removes support for 3.3-V I/O on the L2 cache interface.
Some comments on the MPC7410 with respect to the MPC7400:
•
•
•
Figure 1 shows a block diagram of the MPC7410.
1.2
•
Features
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving two speculations)
— Up to one speculative stream in execution, one additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating
branch delay slots
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU)
— Serialization control (predispatch, postdispatch, execution serialization)
This section summarizes features of the MPC7410 implementation of the PowerPC architecture. Major
features of the MPC7410 are as follows:
•
2
MPC7410 RISC Microprocessor Hardware Specifications
MOTOROLA
Instruction Unit
128-Bit
(4 Instructions)
Fetcher
BTIC
(64-Entry)
128-Entry
ITLB
Data MMU
EA
SRs
(Original)
DBAT
Array
128-Entry
DTLB
Dispatch Unit
PA
64-Bit (2 Instructions)
32-Kbyte
Tags D Cache
LR
CTR
BHT
(512-Entry)
IBAT
Array
Tags
Branch Processing
Unit
SRs
(Shadow)
MOTOROLA
Instruction MMU
Instruction Queue
(6-Word)
32-Kbyte
I Cache
Reservation
Station
VR File
6 Rename
Buffers
Integer
Unit 1
Integer
Unit 2
System
Register Unit
6 Rename
Buffers
GPR File
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station (2-Entry)
FPR File
6 Rename
Buffers
Load/Store Unit
+
(EA Calculation)
Load Fold
Finished Queue
32-Bit
Stores
Reservation
Station
Vector ALU
Floating-
Point Unit
•
•
•
•
•
•
Additional Features
Time Base
Counter/Decrementer
Clock Multiplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
2 Instructions
Reservation
Station
Vector
Permute
Unit
VSIU VCIU VFPU
+ x ÷
32-Bit
128-Bit
128-Bit
32-Bit
+
+ x ÷
FPSCR
FPSCR
Figure 1. MPC7410 Block Diagram
Vector
Touch
Queue
VSCR
Completed
L1
Stores Operations 64-Bit
64-Bit
MPC7410 RISC Microprocessor Hardware Specifications
L2 Controller
L2 Data
L2 Tags
Transaction
L2CR
Queue
L2PMCR
Ability to Complete Up
to Two Instructions Per Clock
19-Bit L2 Address Bus
64- or 32-Bit L2 Data Bus
32-Bit Address Bus
64-Bit Data Bus
Bus Interface Unit
Data
L2 Miss
Transaction
Queue
L2 Castout
Completion Unit
Memory Subsystem
Data Reload Data Reload
Buffer
Table
Completion Queue
(8-Entry)
Instruction
Instruction
Reload Buffer Reload Table
Features
3
Features
•
•
•
•
•
•
•
Decode
— Register file access
— Forwarding control
— Partial instruction decode
Completion
— Eight-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization, and all instruction flow changes
Fixed point units (FXUs) that share 32 GPRs for integer operands
— Fixed point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
Three-stage floating-point unit and a 32-entry FPR file
— Support for IEEE-754 standard single- and double-precision floating-point arithmetic
— Three-cycle latency, one-cycle throughput (single- or double-precision)
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
AltiVec unit
— Full 128-bit data paths
— Two dispatchable units: vector permute unit and vector ALU unit.
— Contains its own 32-entry 128-bit vector register file (VRF) with 6 renames
— The vector ALU unit is further subdivided into the vector simple integer unit (VSIU), the vector
complex integer unit (VCIU), and the vector floating-point unit (VFPU).
— Fully pipelined
Load/store unit
— One-cycle load or store cache access (byte, half word, word, double word)
— Two-cycle load latency with 1-cycle throughput
— Effective address generation
— Hits under misses (multiple outstanding misses)
— Single-cycle unaligned access within double-word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
4
MPC7410 RISC Microprocessor Hardware Specifications
MOTOROLA
Features
•
•
•
•
— Executes the cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian supported
— Supports FXU, FPU, and AltiVec load/store traffic
— Complete support for all four architecture AltiVec DST streams
Level 1 (L1) cache structure
— 32K, 32-byte line, eight-way set-associative instruction cache (iL1)
— 32K, 32-byte line, eight-way set-associative data cache (dL1)
— Single-cycle cache access
— Pseudo least-recently-used (LRU) replacement
— Data cache supports AltiVec LRU and transient instructions algorithm
— Copy-back or write-through data cache (on a page-per-page basis)
— Supports all PowerPC memory coherency modes
— Nonblocking instruction and data cache
— Separate copy of data cache tags for efficient snooping
— No snooping of instruction cache except for ICBI instruction
Level 2 (L2) cache interface
— Internal L2 cache controller and tags; external data SRAMs
— 512K, 1M, and 2-Mbyte two-way set-associative L2 cache support
— Copy-back or write-through data cache (on a page basis, or for all L2)
— 32-byte (512-K), 64-byte (1-M), or 128-byte (2-M) sectored line size
— Supports pipelined (register-register) synchronous BurstRAMs and pipelined (register-register)
late write synchronous BurstRAMs
— Supports direct-mapped mode for 256K, 512K, 1M, or 2-Mbyte of SRAM (either all, half, or
none of L2 SRAM must be configured as direct-mapped)
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
— 64-bit data bus which also supports 32-bit bus mode
— Selectable interface voltages of 1.8 and 2.5 V
Memory management unit
— 128-entry, two-way set-associative instruction TLB
— 128-entry, two-way set-associative data TLB
— Hardware reload for TLBs
— Four instruction BATs and four data BATs
— Virtual memory support for up to 4 exabytes (2
52
) of virtual memory
— Real memory support for up to 4 gigabytes (2
32
) of physical memory
— Snooped and invalidated for TLBI instructions
Efficient data flow
— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide
— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF
— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
— Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus
MOTOROLA
MPC7410 RISC Microprocessor Hardware Specifications
5
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