ISM Band
FSK Receiver IC
ADF7902
FEATURES
Single-chip, low power UHF receiver
Companion receiver to ADF7901 transmitter
Frequency range: 369.5 MHz to 395.9 MHz
Eight RF channels selectable with three digital inputs
Modulation parameters supported
FSK demodulation
2 kbps data rate
34.8 kHz frequency deviation
5.0 V supply voltage
Low power consumption
18.5 mA with receiver enabled
1 μA standby current
24-lead TSSOP
GENERAL DESCRIPTION
The ADF7902 is a low power UHF receiver. The device demodu-
lates frequency shift keyed (FSK) signals with 34.8 kHz frequency
deviation and at data rates of up to 2 kbps. There are eight specific
RF channels ranging from 369.5 MHz to 395.9 MHz on which the
receiver can operate. Each channel is selectable by configuring
three digital control lines.
The ADF7902 is designed for low power applications, consuming
18.5 mA (typical) during normal operation and 1 μA (maximum)
in standby mode.
FUNCTIONAL BLOCK DIAGRAM
GND
CE
ADF7902
LNA_1
LNA
LNA_2
IF FILTER
FSK
DEMODULATOR
Rx_DATA
VBAT1
CREG1
VBAT2
CREG2
LDO1
CH1_SEL
N DIVIDER
SELECT
LDO2
CH2_SEL
CH3_SEL
VCO
LNA_RSET
BIAS
CP
PFD
OSC
CLKOUT
CLKOUT_ENB
06456-001
RSET
CVCO
VCOIN
CPOUT
OSC1 OSC2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADF7902
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ..............................................6
Applications Information .................................................................7
Applications Circuits ....................................................................7
Test Modes..........................................................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADF7902
SPECIFICATIONS
V
DD
=5.0 V; GND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical specifications T
A
= 25°C.
Table 1.
Parameter
CHANNEL FREQUENCIES
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
RECEIVER PARAMETERS
Data Rate
Frequency Deviation
Input Sensitivity
LNA Input Impedance
CHANNEL FILTERING
IF Filter Bandwidth
Adjacent Channel Rejection
Min
Typ
369.5
371.1
375.3
376.9
388.3
391.5
394.3
395.9
2
−34.8
+34.8
−110
128 − j125
200
60
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kbps
kHz
kHz
dBm
Ω
kHz
dB
Test Conditions
Data = 0
Data = 1
f
RF
= 388.3 MHz
−3 dB bandwidth
1 MHz offset
Desired signal 3 dB above input sensitivity level,
with interferer power increased until BER = 10
−3
PHASE-LOCKED LOOP
CE High to Receive Data
REFERENCE INPUT
Crystal Reference
INPUT LOGIC LEVELS
Input High Voltage, V
IH
Input Low Voltage, V
IL
OUTPUT LOGIC LEVELS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output Drive Level
POWER SUPPLY
Voltage Supply
V
DD
Current Consumption
Receiver Enabled
Low Power Sleep Mode
4
9.8304
0.7 × V
DD
0.2 × V
DD
4.5
0.4
2
ms
MHz
V
V
V
V
mA
±25 ppm frequency accuracy
5
18.5
1
V
mA
μA
CE = 1
CE = 0
Rev. 0 | Page 3 of 12
ADF7902
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 2.
Parameter
VBAT to GND
1
Digital I/O Voltage to GND
LNA_1, LNA_2
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θ
JA
Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to +6.0 V
−0.3 V to VBAT + 0.3 V
0 dBm
−40°C to +85°C
−40°C to +125°C
125°C
150.4°C/W
235°C
240°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
GND = GND1 = GND1B = GND2 = 0 V.
Rev. 0 | Page 4 of 12
ADF7902
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CREG2
1
TEST
2
VBAT2
3
CE
4
Rx_DATA
5
GND1
6
CH1_SEL
CH2_SEL
7
8
24
VCOIN
23
GND2
22
CVCO
21
RSET
19
LNA_1
TOP VIEW
(Not to Scale)
18
LNA_2
17
CREG1
16
VBAT1
15
OSC1
14
OSC2
06456-002
ADF7902
20
LNA_RSET
CLKOUT
9
CH3_SEL
10
CLKOUT_ENB
11
CPOUT
12
13
GND1B
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
Mnemonic
CREG2
TEST
VBAT2
CE
Rx_DATA
GND1
CH1_SEL
CH2_SEL
CLKOUT
Description
A 0.1 μF capacitor should be added at CREG2 to reduce regulator noise and improve stability. A reduced
capacitor improves regulator power-on time but may cause higher spurs.
Test Output Pin. Leave as no connect.
5 V Power Supply for RF Circuitry. Decoupling capacitors to the analog ground plane should be placed as close
as possible to this pin.
Chip Enable Input. Driving CE low puts the part into power-down mode, drawing <1 μA.
Receiver Output. Demodulated data appears on this pin.
Ground for Digital Circuitry.
Channel Select Pin. This represents the LSB of the channel select pins.
Channel Select Pin.
Square Wave Clock Output at the Crystal Frequency. This can be used to drive the OSC2 pin of a partnering
ADF7902. The output has a 50:50 mark-space ratio and switches between 0 V and 2.2 V. If CLKOUT is disabled
by setting Pin 11 high, then CLKOUT must be tied low.
Channel Select Pin.
CLKOUT Enable Input. This should be driven low to enable the reference clock signal to appear on the CLKOUT pin.
Driving the pin high removes the clock signal on CLKOUT. It should be driven high when an external reference is used.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
Ground for Digital Circuitry.
The reference crystal should be connected between this pin and OSC1. The necessary crystal load capacitor
should be tied between this pin and ground. A square wave signal can be applied to this pin as an external
reference source.
The reference crystal should be connected between this pin and OSC2. The necessary crystal load capacitor
should be tied between this pin and ground. This pin should be connected to ground when OSC2 is driven by an
external reference.
5 V Power Supply for Digital Circuitry. Decoupling capacitors to the analog ground plane should be placed as
close as possible to this pin.
A 0.1 μF capacitor should be added at CREG1 to reduce regulator noise and improve stability. A reduced
capacitor improves regulator power-on time but may cause higher spurs.
LNA Input. Input matching is required between the antenna and the differential LNA input to ensure maximum
power transfer.
Complementary LNA Input.
External Bias Resistor for LNA. A value of 1.1 kΩ is recommended.
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. A value of 3.6 kΩ is recommended.
Voltage Controlled Oscillator (VCO) Capacitor. A 22 nF capacitor should be placed between this pin and CREG2
to reduce VCO noise.
Ground for RF Circuitry.
The tuning voltage on this pin determines the output frequency of the VCO. The higher the tuning voltage,
the higher the output frequency. The output of the loop filter is connected here.
Rev. 0 | Page 5 of 12
10
11
12
13
14
CH3_SEL
CLKOUT_ENB
CPOUT
GND1B
OSC2
15
OSC1
16
17
18
19
20
21
22
23
24
VBAT1
CREG1
LNA_2
LNA_1
LNA_RSET
RSET
CVCO
GND2
VCOIN
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