KM44S64230AT-F8 datasheet, PDF

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KM44S64230AT-F8: DescriptionSynchronous DRAM, 64MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54; Categorystorage storage; File Size135KB，11 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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KM44S64230AT-F8 Overview

Synchronous DRAM, 64MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54

KM44S64230AT-F8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	125 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.21 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

KM44S64230AT-F8 Preview

KM44S64230A

CMOS SDRAM

256Mbit SDRAM

16M x 4bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.4

JUN 1999

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.4 JUN 1999

KM44S64230A

Revision History

Revision 0.1 (Jan. 05, 1999)

CMOS SDRAM

• Changed the Current values of ICC1, ICC2P(2PS), ICC3P(3PS), ICC3NS, ICC4, ICC5, ICC6 in DC CHARACTERIS-

TICS.

• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.

Revision 0.2 (Jan. 25, 1999)

• Changed the Current values of ICC1, ICC2, ICC3, ICC4, ICC5, ICC6 in DC CHARACTERISTICS.

• Eliminated Preliminary in Datasheet.

Revision 0.3 (May 15, 1999)

• Add the A(7.5ns)product’ AC and DC CHARACTERISTICS in datasheet.

• Skip the -G0/F0 product in the datasheet.

• Skip ICC4 value of CL=2 in DC characteristics in datasheet.

• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.

• Changed the value of I

• Changed the symbols.

Before

Input leakage current (inputs)

Input leakage current (I/O pins)

Output open @ DC characteristic table

After

Input leakage current

Output open @ DC characteristic table

•

Changed Test Condition in

DC CHARACTERISTIC

Symbol

CC2P ,

CC3P

CC2N ,

CC3N

CC4

Before

CKE

≤

(max), t

= 15ns

CKE

≥

(min), CS

≥

(min), t

= 15ns

Input signals are changed one time during 30ns

2 Banks activated

After

CKE

≤

(max), t

= 10ns

CKE

≥

(min), CS

≥

(min), t

= 10ns

Input signals are changed one time during 20ns

4 Banks activated

Revision 0.4 (Jun 25, 1999)

• Add Notes 5 in OPERATING AC PARAMETER.

For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK+20ns.

Rev. 0.4 JUN 1999

KM44S64230A

16M x 4Bit x 4 Banks Synchronous DRAM

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (8K cycle)

Part No.

KM44S64230AT-G/FA

KM44S64230AT-G/F8

KM44S64230AT-G/FH

KM44S64230AT-G/FL

CMOS SDRAM

GENERAL DESCRIPTION

The KM44S64230A is 268,435,456 bits synchronous high data

rate Dynamic RAM organized as 4 x 16,785,216 words by 4 bits,

fabricated with SAMSUNG's high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the use

of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and

programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system

applications.

ORDERING INFORMATION

Max Freq.

133MHz(CL=3)

125MHz(CL=3)

100MHz(CL=2)

100MHz

LVTTL

54pin

TSOP(II)

Interface Package

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

LDQM

Data Input Register

Bank Select

16M x 4

Sense AMP

16M x 4

Refresh Counter

Output Buffer

Row Decoder

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

Latency & Burst Length

LRAS

LCBR

LCKE

LRAS

LCBR

LWE

LCAS

Timing Register

Programming Register

LWCBR

LDQM

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.4 JUN 1999

KM44S64230A

PIN CONFIGURATION

(Top view)

N.C

DDQ

N.C

DQ0

SSQ

N.C

DDQ

N.C

DQ1

SSQ

N.C

CAS

RAS

BA0

BA1

A10/AP

N.C

SSQ

N.C

DQ3

DDQ

N.C

SSQ

N.C

DQ2

DDQ

N.C

N.C/RFU

DQM

CLK

CKE

A12

A11

CMOS SDRAM

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

CLK

Name

System clock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.

Row address : RA

~ RA

, Column address : CA

~ CA

,CA

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

This pin is recommended to be left No Connection on the device.

CKE

Clock enable

~ A

~ BA

RAS

CAS

DQM

DDQ

SSQ

N.C/RFU

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Data output power/ground

No connection

/reserved for future use

Rev. 0.4 JUN 1999

KM44S64230A

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

, V

DDQ

STG

Value

-1.0 ~ 4.6

-55 ~ +150

CMOS SDRAM

Unit

°C

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

(Recommended

operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Symbol

, V

DDQ

Min

3.0

2.0

-0.3

2.4

-10

Typ

3.3

3.0

Max

3.6

+0.3

0.8

0.4

Unit

= -2mA

= 2mA

Note

Notes :

1. V

(max) = 5.6V AC.The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

Clock

= 3.3V, T

= 23°C, f = 1MHz, V

REF

=1.4V

200 mV)

Symbol

CLK

ADD

OUT

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

RAS, CAS, WE, CS, CKE, DQM

Address

~ DQ

Notes :

1. -A only specify a maximum value of 3.5pF

2. -A only specify a maximum value of 3.8pF

3. -A only specify a maximum value of 6.0pF

Rev. 0.4 JUN 1999

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Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
Contacts	54	54	54	54	54	54	54	54
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns	5.4 ns	5.4 ns	6 ns	6 ns	6 ns	6 ns
Maximum clock frequency (fCLK)	125 MHz	100 MHz	133 MHz	133 MHz	100 MHz	100 MHz	100 MHz	125 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	4	4	4	4	4	4	4	4
Number of functions	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1
Number of terminals	54	54	54	54	54	54	54	54
word count	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words	67108864 words
character code	64000000	64000000	64000000	64000000	64000000	64000000	64000000	64000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	64MX4	64MX4	64MX4	64MX4	64MX4	64MX4	64MX4	64MX4
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
Encapsulate equivalent code	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A
Maximum slew rate	0.21 mA	0.2 mA	0.21 mA	0.21 mA	0.2 mA	0.2 mA	0.2 mA	0.21 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
self refresh	YES	YES	-	-	YES	YES	YES	YES

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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