UPD784927Y datasheet, PDF - EEWORLD Datasheet

DATA SHEET

µ

PD784927, 784928, 784927Y, 784928Y

16-BIT SINGLE-CHIP MICROCONTROLLER

MOS INTEGRATED CIRCUIT

DESCRIPTION

The

µ

PD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high-

speed, high-performance 16-bit CPU for VCR software servo control.

The

µ

PD784927Y and 784928Y are based on the

µ

PD784928 with the addition of an I

2

C bus interface compatible

with multi-master.

They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer

unit) for software servo control and VCR analog circuits.

Flash memory models, the

µ

PD78F4928 and

µ

PD78F4928Y, are under development.

The functions of the

µ

PD784927 is described in detail in the following User’s Manual. Be sure to read this

manual before designing your system.

µ

PD784928, 784928Y Subseries User’s Manual - Hardware

78K/IV Series User’s Manual - Instruction

: U12648E

: U10905E

FEATURES

•

High instruction execution speed realized by 16-bit CPU core

• Minimum instruction execution time: 250 ns (with 8 MHz internal clock)

High internal memory capacity

Item

Part Number

µ

PD784927, 784927Y

96K bytes

2048 bytes

µ

PD784928, 784928Y

128K bytes

3584 bytes

Internal ROM capacity

Internal RAM capacity

•

VCR analog circuits conforming to VHS Standard

• CTL amplifier

• RECCTL driver (rewritable)

• CFG amplifier

• DFG amplifier

• DPG amplifier

• Reel FG comparator (2 channels)

• CSYNC comparator

• DPFG separation circuit (ternary separation circuit)

•

Timer unit (super timer unit) for servo control

Serial interface : 3 channels

3-wire serial I/O : 2 channels

I

2

C bus interface: 1 channel

A/D converter: 12 channels (conversion time: 10

µ

s)

Low-frequency oscillation mode: main system clock frequency = internal clock frequency

Low-power consumption mode: CPU can operate with a subsystem clock.

Supply voltage range: V

DD

= +2.7 to 5.5 V

Hardware watch function: watch operation at low voltage (V

DD

= 2.7 V (MIN.)) and low current consumption

Unless otherwise specified, the

µ

PD784927 is treated as the representative model throughout this document.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

Document No. U12255EJ2V0DS00 (2nd edition)

Date Published December 1999 N CP(K)

Printed in Japan

The mark

shows major revised points.

©

1997,1999

µ

PD784927, 784928, 784927Y, 784928Y

APPLICATION FIELDS

Stationary VCR, video camera, In-TV VCR

ORDERING INFORMATION

(1)

µ

PD784928 subseries

Part Number

Package

100-pin plastic LQFP (fine pitch) (14

×

14 mm)

100-pin plastic QFP (14

×

20 mm)

100-pin plastic LQFP (fine pitch) (14

×

14 mm)

100-pin plastic QFP (14

×

20 mm)

µ

PD784927GC-×××-8EU

Note

µ

PD784927GF-×××-3BA

µ

PD784928GC-×××-8EU

Note

µ

PD784928GF-×××-3BA

(2)

µ

PD784928Y subseries

Part Number

Package

100-pin plastic LQFP (fine pitch) (14

×

14 mm)

100-pin plastic QFP (14

×

20 mm)

100-pin plastic LQFP (fine pitch) (14

×

14 mm)

100-pin plastic QFP (14

×

20 mm)

µ

PD784927YGC-×××-8EU

Note

µ

PD784927YGF-×××-3BA

µ

PD784928YGC-×××-8EU

Note

µ

PD784928YGF-×××-3BA

Note

Under development

Remark

×××

indicates ROM code suffix.

PRODUCT DEVELOPMENT OF VCR-SERVO MICROCONTROLLERS

The product development of VCR-servo microcontrollers is shown below. Enclosed in a frame are subseries

names.

The Y subseries is a collection of products supporting the I

2

C bus.

Products under mass production

Products under development

78K/IV series

µ

PD784928

µ

PD784928Y

100-pin QFP. With flash memory.

Expanded internal memory capacity.

More powerful analog amplifier. Improved VCR functions.

Increased I/O. High-current port added.

I

2

C function added (Y model only).

100-pin QFP.

Expanded internal memory capacity.

Internal analog amplifier. Reinforced super timer.

Low-power consumption mode added.

100-pin QFP

Expanded internal RAM capacity. Operational amplifier,

watch function, multiplier added.

µ

PD784915

78K/I series

µ

PD78148

µ

PD78138

80-pin QFP

2

Data Sheet U12255EJ2V0DS00

µ

PD784927, 784928, 784927Y, 784928Y

FUNCTION LIST (1/2)

Part Number

Item

Internal ROM capacity

Internal RAM capacity

Operating clock

96K bytes

2048 bytes

128K bytes

3584 bytes

µ

PD784927, 784927Y

µ

PD784928, 784928Y

16 MHz (internal clock: 8 MHz)

Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz)

Low power consumption mode : 32.768 kHz (subsystem clock)

250 ns (with 8 MHz internal clock)

Minimum instruction e x e c u -

tion time

I/O port

74

input : 20

I/O

: 54 (including 8 ports for LED direct drive)

Real-time output port

Timer/counter

11 (including one each for pseudo V

SYNC

, head amplifier switch, and chrominance rotation)

Timer/counter

TM0 (16 bits)

TM1 (16 bits)

FRC (22 bits)

TM3 (16 bits)

UDC (5 bits)

EC (8 bits)

EDV (8 bits)

Input signal

CFG

DFG

HSW

V

SYNC

CTL

T

REEL

S

REEL

Compare register

3

—

2

1

4

1

Number of bits

22

16

22

16

22

Capture register

—

1

6

1

—

Measurable cycle

125 ns to 524 ms

1

µ

s to 65.5 ms

125 ns to 524 ms

1

µ

s to 65.5 ms

125 ns to 524 ms

Remark

For HSW signal generation

For CFG signal division

Operating edge

↑

↓

↑

↓

Capture register

Super

timer unit

VCR special

circuit

•

V

SYNC

separation circuit, H

SYNC

separation circuit

VISS detection, wide aspect detection circuits

Field identification circuit

Head amplifier switch/chrominance rotation output circuit

Timer

TM2 (16 bits)

TM4 (16 bits)

TM5 (16 bits)

Compare register

1

1 (capture/compare)

1

Capture register

—

1

—

General-purpose

timer

PWM output

•

16-bit resolution : 3 channels (carrier frequency: 62.5 kHz)

8-bit resolution : 3 channels (carrier frequency: 62.5 kHz)

Serial interface

3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel)

•

I

2

C bus interface: 1 channel (

µ

PD784928Y subseries only)

8-bit resolution

×

12 channels, conversion time: 10

µ

s

A/D converter

Data Sheet U12255EJ2V0DS00

3

µ

PD784927, 784928, 784927Y, 784928Y

FUNCTION LIST (2/2)

Part Number

Item

Analog circuit

•

CTL amplifier

RECCTL driver (rewritable)

DFG amplifier, DPG amplifier, CFG amplifier

DPFG separation circuit (ternary separation circuit)

Reel FG comparator (2 channels)

CSYNC comparator

µ

PD784927, 784927Y

µ

PD784928, 784928Y

Interrupt sources

External

Internal

Standby function

4 levels (programmable), vectored interrupt, macro service, context switching

9 (including NMI)

22 (including software interrupt)

23 (including software interrupt)

HALT mode/STOP mode/low power consumption mode/low power consumption HALT mode

STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/

INTP2/KEY0-KEY4 pins

Watch function

Buzzer output function

0.5-second measurement, low-voltage operation (V

DD

= 2.7 V)

1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Internal clock: 8 MHz)

2.048 kHz, 4.096 kHz, 32.768 kHz (Subsystem clock: 32.768 kHz)

Supply voltage

Package

V

DD

= +2.7 to 5.5 V

• 100-pin plastic LQFP (fine pitch)(14

×

14 mm)

Note

• 100-pin plastic QFP (14

×

20 mm)

Note

Under development

4

Data Sheet U12255EJ2V0DS00

µ

PD784927, 784928, 784927Y, 784928Y

PIN CONFIGURATION (Top View)

•

100-pin plastic LQFP (fine pitch)(14

×

14 mm)

µ

PD784927GC-×××-8EU

Note 1

, 784928GC-×××-8EU

Note 1

µ

PD784928YGC-×××-8EU, 784928YGC-×××-8EU

Note 1

P85/PWM3/SCL

Note 2

P86/PTO10

P87/PTO11

P30/PTO00

P31/PTO01

P32/PTO02

IC

RESET

X1

X2

V

SS

XT2

XT1

V

DD

P33/SI2/BUSY

P34/SO2

P35/SCK2

P36/PWM1

P37/PWM0

P63/SI1

P62/SO1

P61/SCK1/BUZ

P60/STRB/CLO

P67/PWM5/CTLMON

P66/PWM4/CFGMON

P84/PWM2/SDA

Note 2

P83/ROTC

P82/HASW

P80

P57

P56

P55

P54

P53

P52

P51

P50

V

SS

V

DD

P47

P46

P45

P44

P43

P42

P41

P40

P07

P06

P05

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

75

2

74

3

73

4

72

5

71

6

70

7

69

8

68

9

67

10

66

11

65

12

64

13

63

14

62

15

61

16

60

17

59

18

58

19

57

20

56

21

55

22

54

23

53

24

52

25

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P65/HWIN/DPGMON

P64/BUZ/DFGMON

P103/CSYNCIN

P102/REEL0IN/INTP3

P101/REEL1IN

DFGIN

P100/DPGIN

CFGCPIN

CFGAMP0

CFGIN

AV

DD1

AV

SS1

VREFC

CTLOUT2

CTLOUT1

CTLIN

RECCTL−

RECCTL+

CTLDLY

AV

SS2

P113/ANI11

P112/ANI10

P111/ANI9

P110/ANI8

P77/ANI7

Notes 1.

Under development

2.

Pins SCL and SDA are provided for the

µ

PD784928Y subseries only.

Caution Directly connect the IC (Internally Connected) pins to V

SS

in the normal operation mode.

P04

P03

P02

P01

P00

P23/INTP2

P22/INTP1

P21/INTP0

P20/NMI

P90/ENV

P91/KEY0

P92/KEY1

P93/KEY2

P94/KEY3

P95/KEY4

P96

AV

DD2

AV

REF

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

Data Sheet U12255EJ2V0DS00

5

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